1 #define PCI_TRANSLATION_ENABLE 1
3 #include "devices/pci.h"
4 #include "threads/malloc.h"
5 #include "threads/interrupt.h"
6 #include "threads/pte.h"
7 #include "threads/io.h"
8 #include "pci_lookup.h"
15 extern uint32_t *base_page_dir;
17 #define PCI_REG_ADDR 0xcf8
18 #define PCI_REG_DATA 0xcfc
19 #define pci_config_offset(bus, dev, func, reg) (0x80000000 | ((bus) << 16) | ((dev) << 11) | ((func) << 8) | (reg & (~3)))
21 #define PCI_MAX_DEV_PER_BUS 32
22 #define PCI_MAX_FUNC_PER_DEV 8
24 #define PCI_HEADER_SZ 256
26 #define PCI_CMD_IO 0x001 /* enable io response */
27 #define PCI_CMD_MEMORY 0x002 /* enable memory response */
28 #define PCI_CMD_MASTER 0x004 /* enable bus mastering */
29 #define PCI_CMD_SPECIAL 0x008 /* enable special cycles */
30 #define PCI_CMD_INVALIDATE 0x010 /* memory write + invalidate */
31 #define PCI_CMD_PALETTE 0x020 /* palette snooping */
32 #define PCI_CMD_PARITY 0x040 /* parity checking */
33 #define PCI_CMD_WAIT 0x080 /* address/data stepping */
34 #define PCI_CMD_SERR 0x100 /* serr */
35 #define PCI_CMD_FASTBACK 0x200 /* back-to-back writing */
36 #define PCI_CMD_INTX_DISABLE 0x400 /* emulation disable */
38 #define PCI_STATUS_CAPLIST 0x10 /* capability list */
39 #define PCI_STATUS_66MHZ 0x20 /* 66mhz pci 2.1 bus */
40 #define PCI_STATUS_UDF 0x40 /* user definable features */
41 #define PCI_STATUS_FASTBACK 0x80 /* fast back to back */
42 #define PCI_STATUS_PARITY 0x100 /* parity error detected */
43 #define PCI_STATUS_DEVSEL 0x600 /* devsel mask */
44 #define PCI_STATUS_DEVSEL_FAST 0
45 #define PCI_STATUS_DEVSEL_MED 0x200
46 #define PCI_STATUS_DEVSEL_SLOW 0x400
47 #define PCI_STATUS_SIG_ABORT 0x0800 /* set on target abort */
48 #define PCI_STATUS_REC_ABORT 0x1000 /* master ack of abort */
49 #define PCI_STATUS_REC_ABORT_M 0x2000 /* set on master abort */
50 #define PCI_STATUS_SERR 0x4000 /* system error */
51 #define PCI_STATUS_PARITY2 0x8000 /* set on parity err */
53 #define PCI_HEADER_NORMAL 0
54 #define PCI_HEADER_BRIDGE 1
55 #define PCI_HEADER_CARDBUS 2
57 #define PCI_HEADER_MASK 0x7f
58 #define PCI_HEADER_MULTIFUNC 0x80
60 #define pci_get_reg_offset(x) (&(((pci_config_header*)(NULL))->x))
62 #define PCI_VENDOR_INVALID 0xffff
64 #define PCI_BASEADDR_IO 0x00000001
65 #define PCI_BASEADDR_TYPEMASK 0x00000006
66 #define PCI_BASEADDR_32BIT 0x00000000
67 #define PCI_BASEADDR_64BIT 0x00000004
68 #define PCI_BASEADDR_PREFETCH 0x00000008
69 #define PCI_BASEADDR_ADDR32 0xfffffff0
70 #define PCI_BASEADDR_ADDR64 0xfffffffffffffff0
71 #define PCI_BASEADDR_IOPORT 0xfffffffc
75 struct pci_config_header
77 uint16_t pci_vendor_id;
78 uint16_t pci_device_id;
86 uint8_t pci_interface;
90 uint8_t pci_cachelinesz;
92 uint8_t pci_header; /* header type */
93 uint8_t pci_bist; /* self test */
95 uint32_t pci_base_reg[6];
96 uint32_t pci_cis; /* cardbus cis pointer */
97 uint16_t pci_sub_vendor_id;
99 uint32_t pci_rom_addr;
100 uint8_t pci_capabilities;
102 uint8_t pci_int_line;
105 uint8_t pci_max_latency;
110 #define PCI_BASE_COUNT 6
113 struct pci_config_header pch;
114 uint8_t bus, dev, func;
115 int base_reg_size[PCI_BASE_COUNT];
117 pci_handler_func *irq_handler;
118 void *irq_handler_aux;
120 struct list io_ranges;
121 struct list_elem peer;
122 struct list_elem int_peer;
126 { PCI_IO_MEM, PCI_IO_PORT };
128 /* represents a PCI IO range */
132 enum pci_io_type type;
133 size_t size; /* bytes in range */
136 void *ptr; /* virtual memory address */
137 int port; /* io port */
139 struct list_elem peer; /* linkage */
143 static void pci_write_config (int bus, int dev, int func, int reg,
144 int size, uint32_t data);
145 static uint32_t pci_read_config (int bus, int dev, int func, int reg,
147 static void pci_read_all_config (int bus, int dev, int func,
148 struct pci_config_header *pch);
149 static int pci_scan_bus (int bus);
150 static int pci_probe (int bus, int dev, int func,
151 struct pci_config_header *ph);
152 static int pci_pci_bridge (struct pci_dev *pd);
153 static void pci_power_on (struct pci_dev *pd);
154 static void pci_setup_io (struct pci_dev *pd);
155 static void pci_interrupt (struct intr_frame *);
156 static void pci_print_dev_info (struct pci_dev *pd);
157 static void *pci_alloc_mem (void *phys_ptr, int pages);
159 static struct list devices;
160 static struct list int_devices;
162 /* number of pages that have been allocated to pci devices in the pci zone */
163 static int num_pci_pages;
168 list_init (&devices);
169 list_init (&int_devices);
178 pci_get_device (int vendor, int device, int func, int n)
184 e = list_begin (&devices);
185 while (e != list_end (&devices))
189 pd = list_entry (e, struct pci_dev, peer);
190 if (pd->pch.pci_vendor_id == vendor && pd->pch.pci_device_id == device)
191 if (pd->func == func)
205 pci_get_dev_by_class (int major, int minor, int iface, int n)
211 e = list_begin (&devices);
212 while (e != list_end (&devices))
216 pd = list_entry (e, struct pci_dev, peer);
217 if (pd->pch.pci_major == major && pd->pch.pci_minor == minor &&
218 pd->pch.pci_interface == iface)
233 pci_io_enum (struct pci_dev *pio, struct pci_io *last)
238 e = list_next (&last->peer);
240 e = list_begin (&pio->io_ranges);
242 if (e == list_end (&pio->io_ranges))
245 return list_entry (e, struct pci_io, peer);
249 pci_register_irq (struct pci_dev *pd, pci_handler_func * f, void *aux)
253 ASSERT (pd->irq_handler == NULL);
255 pd->irq_handler_aux = aux;
257 int_vec = pd->pch.pci_int_line + 0x20;
259 list_push_back (&int_devices, &pd->int_peer);
261 /* ensure that pci interrupt is hooked */
262 if (!intr_is_registered (int_vec))
263 intr_register_ext (int_vec, pci_interrupt, "PCI");
267 pci_unregister_irq (struct pci_dev *pd)
272 list_remove (&pd->int_peer);
275 pd->irq_handler = NULL;
276 pd->irq_handler_aux = NULL;
280 pci_io_size (struct pci_io *pio)
282 ASSERT (pio != NULL);
288 pci_reg_write32 (struct pci_io *pio, int reg, uint32_t data)
290 ASSERT (pio != NULL);
291 ASSERT ((unsigned) reg < pio->size);
293 if (pio->type == PCI_IO_MEM)
295 *((uint32_t *) (pio->addr.ptr + reg)) = data;
297 else if (pio->type == PCI_IO_PORT)
299 outl (pio->addr.port + reg, data);
302 PANIC ("pci: Invalid IO type\n");
306 pci_reg_write16 (struct pci_io *pio, int reg, uint16_t data)
308 ASSERT (pio != NULL);
309 ASSERT ((unsigned) reg < pio->size);
311 if (pio->type == PCI_IO_MEM)
313 *((uint16_t *) (pio->addr.ptr + reg)) = data;
315 else if (pio->type == PCI_IO_PORT)
317 outw (pio->addr.port + reg, data);
320 PANIC ("pci: Invalid IO type\n");
324 pci_reg_write8 (struct pci_io *pio, int reg, uint8_t data)
326 ASSERT (pio != NULL);
327 ASSERT ((unsigned) reg < pio->size);
329 if (pio->type == PCI_IO_MEM)
331 *((uint8_t *) (pio->addr.ptr + reg)) = data;
333 else if (pio->type == PCI_IO_PORT)
335 outb (pio->addr.port + reg, data);
338 PANIC ("pci: Invalid IO type\n");
342 pci_reg_read32 (struct pci_io *pio, int reg)
346 ASSERT (pio != NULL);
347 ASSERT ((unsigned) reg < pio->size);
349 if (pio->type == PCI_IO_MEM)
351 ret = *((uint32_t *) (pio->addr.ptr + reg));
353 else if (pio->type == PCI_IO_PORT)
355 ret = inl (pio->addr.port + reg);
358 PANIC ("pci: Invalid IO type\n");
364 pci_reg_read16 (struct pci_io * pio, int reg)
368 ASSERT (pio != NULL);
369 ASSERT ((unsigned) reg < pio->size);
372 if (pio->type == PCI_IO_MEM)
374 ret = *((uint16_t *) (pio->addr.ptr + reg));
376 else if (pio->type == PCI_IO_PORT)
378 ret = inw (pio->addr.port + reg);
381 PANIC ("pci: Invalid IO type\n");
388 pci_reg_read8 (struct pci_io * pio, int reg)
392 ASSERT (pio != NULL);
393 ASSERT ((unsigned) reg < pio->size);
395 if (pio->type == PCI_IO_MEM)
397 ret = *((uint8_t *) (pio->addr.ptr + reg));
399 else if (pio->type == PCI_IO_PORT)
401 ret = inb (pio->addr.port + reg);
404 PANIC ("pci: Invalid IO type\n");
410 pci_read_in (struct pci_io *pio UNUSED, int off UNUSED, size_t size UNUSED,
413 PANIC ("pci_read_in: STUB");
417 pci_write_out (struct pci_io *pio UNUSED, int off UNUSED, size_t size UNUSED,
418 const void *buf UNUSED)
420 PANIC ("pci_write_out: STUB");
424 pci_write_config (int bus, int dev, int func, int reg,
425 int size, uint32_t data)
429 config_offset = pci_config_offset (bus, dev, func, reg);
431 outl (PCI_REG_ADDR, config_offset);
436 outb (PCI_REG_DATA + (reg & 3), data);
440 outw (PCI_REG_DATA + (reg & 3), data);
444 outl (PCI_REG_DATA, data);
450 pci_read_config (int bus, int dev, int func, int reg, int size)
455 config_offset = pci_config_offset (bus, dev, func, reg);
457 outl (PCI_REG_ADDR, config_offset);
462 ret = inb (PCI_REG_DATA);
465 ret = inw (PCI_REG_DATA);
468 ret = inl (PCI_REG_DATA);
471 PANIC ("pci: Strange config read size\n");
477 /* read entire configuration header into memory */
479 pci_read_all_config (int bus, int dev, int func,
480 struct pci_config_header *pch)
483 for (i = 0; i < ((sizeof (struct pci_config_header) + 3) & ~3) / 4; i++)
485 ((uint32_t *) pch)[i] = pci_read_config (bus, dev, func, i * 4, 4);
490 /** scan PCI bus for all devices */
492 pci_scan_bus (int bus)
499 for (dev = 0; dev < PCI_MAX_DEV_PER_BUS; dev++)
501 struct pci_config_header pch;
504 pci_read_all_config (bus, dev, 0, &pch);
506 if (pch.pci_vendor_id == PCI_VENDOR_INVALID)
510 if (!(pch.pci_header & PCI_HEADER_MULTIFUNC))
515 for (func = 0; func < func_cnt; func++)
518 retbus = pci_probe (bus, dev, func, &pch);
519 if (retbus > max_bus)
527 /* get all information for a PCI device given bus/dev/func
528 add pci device to device list if applicable
529 return a new bus number if new bus is found
532 pci_probe (int bus, int dev, int func, struct pci_config_header *ph)
538 pci_read_all_config (bus, dev, func, ph);
539 if (ph->pci_vendor_id == PCI_VENDOR_INVALID)
543 pd = malloc (sizeof (struct pci_dev));
544 memcpy (&pd->pch, ph, sizeof (struct pci_config_header));
545 pd->irq_handler = NULL;
546 pd->irq_handler_aux = NULL;
551 list_init (&pd->io_ranges);
552 list_push_back (&devices, &pd->peer);
555 if (ph->pci_major == PCI_MAJOR_BRIDGE)
557 if (ph->pci_minor == PCI_MINOR_PCI)
558 return pci_pci_bridge (pd);
568 pci_setup_io (struct pci_dev *pd)
571 for (i = 0; i < PCI_BASE_COUNT; i++)
576 if (pd->pch.pci_base_reg[i] == 0)
581 /* determine io granularity.. */
582 pci_write_config (pd->bus, pd->dev, pd->func,
583 offsetof (struct pci_config_header, pci_base_reg[i]),
587 pci_read_config (pd->bus, pd->dev, pd->func,
588 offsetof (struct pci_config_header, pci_base_reg[i]),
591 /* configure BAR to the default */
592 pci_write_config (pd->bus, pd->dev, pd->func,
593 offsetof (struct pci_config_header, pci_base_reg[i]),
594 4, pd->pch.pci_base_reg[i]);
596 pio = malloc (sizeof (struct pci_io));
599 if (tmp & PCI_BASEADDR_IO)
601 pio->type = PCI_IO_PORT;
602 pio->size = (uint16_t) ((~tmp + 1) & 0xffff) + 1;
603 pio->addr.port = pd->pch.pci_base_reg[i] & ~1;
609 pio->type = PCI_IO_MEM;
610 pio->size = ROUND_UP ((~tmp + 1), PGSIZE);
611 ofs = (pd->pch.pci_base_reg[i] & 0xfffffff0 & PGMASK);
612 pio->addr.ptr = pci_alloc_mem ((void *) pd->pch.pci_base_reg[i],
614 if (pio->addr.ptr == NULL)
616 printf ("PCI: %d pages for %d:%d.%d failed - may not work\n",
617 pio->size / PGSIZE, pd->bus, pd->dev, pd->func);
623 pio->addr.ptr = (void *) ((uintptr_t) pio->addr.ptr + ofs);
627 /* add IO struct to device, if valid */
629 list_push_back (&pd->io_ranges, &pio->peer);
635 pci_power_on (struct pci_dev *pd UNUSED)
641 pci_pci_bridge (struct pci_dev *pd)
646 /* put bus into offline mode */
647 command = pd->pch.pci_command;
649 pci_write_config (pd->bus, pd->dev, pd->func,
650 offsetof (struct pci_config_header, pci_command),
652 pd->pch.pci_command = command;
654 /* set up primary bus */
655 pci_write_config (pd->bus, pd->dev, pd->func, 0x18, 1, pd->bus);
657 pci_write_config (pd->bus, pd->dev, pd->func, 0x19, 1, pd->bus + 1);
659 /* disable subordinates */
660 pci_write_config (pd->bus, pd->dev, pd->func, 0x1a, 1, 0xff);
662 /* scan this new bus */
663 max_bus = pci_scan_bus (pd->bus + 1);
665 /* set subordinate to the actual last bus */
666 pci_write_config (pd->bus, pd->dev, pd->func, 0x1a, 1, max_bus);
670 pci_write_config (pd->bus, pd->dev, pd->func,
671 offsetof (struct pci_config_header, pci_command),
673 pd->pch.pci_command = command;
678 /* alert all PCI devices waiting on interrupt line that IRQ fired */
680 pci_interrupt (struct intr_frame *frame)
685 int_line = frame->vec_no - 0x20;
686 e = list_begin (&int_devices);
687 while (e != list_end (&int_devices))
691 pd = list_entry (e, struct pci_dev, int_peer);
692 if (pd->pch.pci_int_line == int_line)
693 pd->irq_handler (pd->irq_handler_aux);
698 /* display information on all USB devices */
700 pci_print_stats (void)
704 e = list_begin (&devices);
705 while (e != list_end (&devices))
709 pd = list_entry (e, struct pci_dev, peer);
710 pci_print_dev_info (pd);
717 pci_print_dev_info (struct pci_dev *pd)
719 printf ("PCI Device %d:%d.%d (%x,%x): %s - %s (%s) IRQ %d\n",
720 pd->bus, pd->dev, pd->func,
721 pd->pch.pci_vendor_id,
722 pd->pch.pci_device_id,
723 pci_lookup_vendor (pd->pch.pci_vendor_id),
724 pci_lookup_device (pd->pch.pci_vendor_id, pd->pch.pci_device_id),
725 pci_lookup_class (pd->pch.pci_major, pd->pch.pci_minor,
726 pd->pch.pci_interface), pd->pch.pci_int_line);
730 pci_mask_irq (struct pci_dev *pd)
732 intr_irq_mask (pd->pch.pci_int_line);
736 pci_unmask_irq (struct pci_dev *pd)
738 intr_irq_unmask (pd->pch.pci_int_line);
742 pci_write_config16 (struct pci_dev *pd, int off, uint16_t data)
744 pci_write_config (pd->bus, pd->dev, pd->func, off, 2, data);
748 pci_write_config32 (struct pci_dev *pd, int off, uint32_t data)
750 pci_write_config (pd->bus, pd->dev, pd->func, off, 4, data);
754 pci_write_config8 (struct pci_dev *pd, int off, uint8_t data)
756 pci_write_config (pd->bus, pd->dev, pd->func, off, 1, data);
760 pci_read_config8 (struct pci_dev *pd, int off)
762 return pci_read_config (pd->bus, pd->dev, pd->func, off, 1);
766 pci_read_config16 (struct pci_dev * pd, int off)
768 return pci_read_config (pd->bus, pd->dev, pd->func, off, 2);
772 pci_read_config32 (struct pci_dev * pd, int off)
774 return pci_read_config (pd->bus, pd->dev, pd->func, off, 4);
778 /** allocate PCI memory pages for PCI devices */
780 pci_alloc_mem (void *phys_ptr, int pages)
785 phys_ptr = (void *) ((uintptr_t) phys_ptr & ~PGMASK);
787 /* not enough space to allocate? */
788 if ((unsigned) (num_pci_pages + pages) >= (unsigned) PCI_ADDR_ZONE_PAGES)
793 /* insert into PCI_ZONE */
794 for (i = 0; i < pages; i++)
796 uint32_t pte_idx = (num_pci_pages + i) % 1024;
797 uint32_t pde_idx = (num_pci_pages + i) / 1024;
801 pde_idx += pd_no ((void *) PCI_ADDR_ZONE_BEGIN);
802 pte = ((uint32_t) phys_ptr + (i * PGSIZE)) | PTE_P | PTE_W | PTE_CD;
803 pt = (uint32_t *) (ptov (base_page_dir[pde_idx] & ~PGMASK));
807 vaddr = (void *) (PCI_ADDR_ZONE_BEGIN + (num_pci_pages * PGSIZE));
808 num_pci_pages += pages;