1 #define PCI_TRANSLATION_ENABLE 1
3 #include "devices/pci.h"
4 #include "threads/init.h"
5 #include "threads/malloc.h"
6 #include "threads/interrupt.h"
7 #include "threads/pte.h"
8 #include "threads/io.h"
9 #include "pci_lookup.h"
16 extern uint32_t *base_page_dir;
18 #define PCI_REG_ADDR 0xcf8
19 #define PCI_REG_DATA 0xcfc
20 #define pci_config_offset(bus, dev, func, reg) (0x80000000 | ((bus) << 16) | ((dev) << 11) | ((func) << 8) | (reg & (~3)))
22 #define PCI_MAX_DEV_PER_BUS 32
23 #define PCI_MAX_FUNC_PER_DEV 8
25 #define PCI_HEADER_SZ 256
27 #define PCI_CMD_IO 0x001 /* enable io response */
28 #define PCI_CMD_MEMORY 0x002 /* enable memory response */
29 #define PCI_CMD_MASTER 0x004 /* enable bus mastering */
30 #define PCI_CMD_SPECIAL 0x008 /* enable special cycles */
31 #define PCI_CMD_INVALIDATE 0x010 /* memory write + invalidate */
32 #define PCI_CMD_PALETTE 0x020 /* palette snooping */
33 #define PCI_CMD_PARITY 0x040 /* parity checking */
34 #define PCI_CMD_WAIT 0x080 /* address/data stepping */
35 #define PCI_CMD_SERR 0x100 /* serr */
36 #define PCI_CMD_FASTBACK 0x200 /* back-to-back writing */
37 #define PCI_CMD_INTX_DISABLE 0x400 /* emulation disable */
39 #define PCI_STATUS_CAPLIST 0x10 /* capability list */
40 #define PCI_STATUS_66MHZ 0x20 /* 66mhz pci 2.1 bus */
41 #define PCI_STATUS_UDF 0x40 /* user definable features */
42 #define PCI_STATUS_FASTBACK 0x80 /* fast back to back */
43 #define PCI_STATUS_PARITY 0x100 /* parity error detected */
44 #define PCI_STATUS_DEVSEL 0x600 /* devsel mask */
45 #define PCI_STATUS_DEVSEL_FAST 0
46 #define PCI_STATUS_DEVSEL_MED 0x200
47 #define PCI_STATUS_DEVSEL_SLOW 0x400
48 #define PCI_STATUS_SIG_ABORT 0x0800 /* set on target abort */
49 #define PCI_STATUS_REC_ABORT 0x1000 /* master ack of abort */
50 #define PCI_STATUS_REC_ABORT_M 0x2000 /* set on master abort */
51 #define PCI_STATUS_SERR 0x4000 /* system error */
52 #define PCI_STATUS_PARITY2 0x8000 /* set on parity err */
54 #define PCI_HEADER_NORMAL 0
55 #define PCI_HEADER_BRIDGE 1
56 #define PCI_HEADER_CARDBUS 2
58 #define PCI_HEADER_MASK 0x7f
59 #define PCI_HEADER_MULTIFUNC 0x80
61 #define pci_get_reg_offset(x) (&(((pci_config_header*)(NULL))->x))
63 #define PCI_VENDOR_INVALID 0xffff
65 #define PCI_BASEADDR_IO 0x00000001
66 #define PCI_BASEADDR_TYPEMASK 0x00000006
67 #define PCI_BASEADDR_32BIT 0x00000000
68 #define PCI_BASEADDR_64BIT 0x00000004
69 #define PCI_BASEADDR_PREFETCH 0x00000008
70 #define PCI_BASEADDR_ADDR32 0xfffffff0
71 #define PCI_BASEADDR_ADDR64 0xfffffffffffffff0
72 #define PCI_BASEADDR_IOPORT 0xfffffffc
76 struct pci_config_header
78 uint16_t pci_vendor_id;
79 uint16_t pci_device_id;
87 uint8_t pci_interface;
91 uint8_t pci_cachelinesz;
93 uint8_t pci_header; /* header type */
94 uint8_t pci_bist; /* self test */
96 uint32_t pci_base_reg[6];
97 uint32_t pci_cis; /* cardbus cis pointer */
98 uint16_t pci_sub_vendor_id;
100 uint32_t pci_rom_addr;
101 uint8_t pci_capabilities;
103 uint8_t pci_int_line;
106 uint8_t pci_max_latency;
111 #define PCI_BASE_COUNT 6
114 struct pci_config_header pch;
115 uint8_t bus, dev, func;
116 int base_reg_size[PCI_BASE_COUNT];
118 pci_handler_func *irq_handler;
119 void *irq_handler_aux;
121 struct list io_ranges;
122 struct list_elem peer;
123 struct list_elem int_peer;
127 { PCI_IO_MEM, PCI_IO_PORT };
129 /* represents a PCI IO range */
133 enum pci_io_type type;
134 size_t size; /* bytes in range */
137 void *ptr; /* virtual memory address */
138 int port; /* io port */
140 struct list_elem peer; /* linkage */
144 static void pci_write_config (int bus, int dev, int func, int reg,
145 int size, uint32_t data);
146 static uint32_t pci_read_config (int bus, int dev, int func, int reg,
148 static void pci_read_all_config (int bus, int dev, int func,
149 struct pci_config_header *pch);
150 static int pci_scan_bus (int bus);
151 static int pci_probe (int bus, int dev, int func,
152 struct pci_config_header *ph);
153 static int pci_pci_bridge (struct pci_dev *pd);
154 static void pci_power_on (struct pci_dev *pd);
155 static void pci_setup_io (struct pci_dev *pd);
156 static void pci_interrupt (struct intr_frame *);
157 static void pci_print_dev_info (struct pci_dev *pd);
158 static void *pci_alloc_mem (void *phys_ptr, int pages);
160 static struct list devices;
161 static struct list int_devices;
163 /* number of pages that have been allocated to pci devices in the pci zone */
164 static int num_pci_pages;
169 list_init (&devices);
170 list_init (&int_devices);
179 pci_get_device (int vendor, int device, int func, int n)
185 e = list_begin (&devices);
186 while (e != list_end (&devices))
190 pd = list_entry (e, struct pci_dev, peer);
191 if (pd->pch.pci_vendor_id == vendor && pd->pch.pci_device_id == device)
192 if (pd->func == func)
206 pci_get_dev_by_class (int major, int minor, int iface, int n)
212 e = list_begin (&devices);
213 while (e != list_end (&devices))
217 pd = list_entry (e, struct pci_dev, peer);
218 if (pd->pch.pci_major == major && pd->pch.pci_minor == minor &&
219 pd->pch.pci_interface == iface)
234 pci_io_enum (struct pci_dev *pio, struct pci_io *last)
239 e = list_next (&last->peer);
241 e = list_begin (&pio->io_ranges);
243 if (e == list_end (&pio->io_ranges))
246 return list_entry (e, struct pci_io, peer);
250 pci_register_irq (struct pci_dev *pd, pci_handler_func * f, void *aux)
254 ASSERT (pd->irq_handler == NULL);
256 pd->irq_handler_aux = aux;
258 int_vec = pd->pch.pci_int_line + 0x20;
260 list_push_back (&int_devices, &pd->int_peer);
262 /* ensure that pci interrupt is hooked */
263 if (!intr_is_registered (int_vec))
264 intr_register_ext (int_vec, pci_interrupt, "PCI");
268 pci_unregister_irq (struct pci_dev *pd)
273 list_remove (&pd->int_peer);
276 pd->irq_handler = NULL;
277 pd->irq_handler_aux = NULL;
281 pci_io_size (struct pci_io *pio)
283 ASSERT (pio != NULL);
289 pci_reg_write32 (struct pci_io *pio, int reg, uint32_t data)
291 ASSERT (pio != NULL);
292 ASSERT ((unsigned) reg < pio->size);
294 if (pio->type == PCI_IO_MEM)
296 *((uint32_t *) (pio->addr.ptr + reg)) = data;
298 else if (pio->type == PCI_IO_PORT)
300 outl (pio->addr.port + reg, data);
303 PANIC ("pci: Invalid IO type\n");
307 pci_reg_write16 (struct pci_io *pio, int reg, uint16_t data)
309 ASSERT (pio != NULL);
310 ASSERT ((unsigned) reg < pio->size);
312 if (pio->type == PCI_IO_MEM)
314 *((uint16_t *) (pio->addr.ptr + reg)) = data;
316 else if (pio->type == PCI_IO_PORT)
318 outw (pio->addr.port + reg, data);
321 PANIC ("pci: Invalid IO type\n");
325 pci_reg_write8 (struct pci_io *pio, int reg, uint8_t data)
327 ASSERT (pio != NULL);
328 ASSERT ((unsigned) reg < pio->size);
330 if (pio->type == PCI_IO_MEM)
332 ((uint8_t *) pio->addr.ptr)[reg] = data;
334 else if (pio->type == PCI_IO_PORT)
336 outb (pio->addr.port + reg, data);
339 PANIC ("pci: Invalid IO type\n");
343 pci_reg_read32 (struct pci_io *pio, int reg)
347 ASSERT (pio != NULL);
348 ASSERT ((unsigned) reg < pio->size);
350 if (pio->type == PCI_IO_MEM)
352 ret = ((uint32_t *) pio->addr.ptr)[reg];
354 else if (pio->type == PCI_IO_PORT)
356 ret = inl (pio->addr.port + reg);
359 PANIC ("pci: Invalid IO type\n");
365 pci_reg_read16 (struct pci_io * pio, int reg)
369 ASSERT (pio != NULL);
370 ASSERT ((unsigned) reg < pio->size);
373 if (pio->type == PCI_IO_MEM)
375 ret = ((uint16_t *) pio->addr.ptr)[reg];
377 else if (pio->type == PCI_IO_PORT)
379 ret = inw (pio->addr.port + reg);
382 PANIC ("pci: Invalid IO type\n");
389 pci_reg_read8 (struct pci_io * pio, int reg)
393 ASSERT (pio != NULL);
394 ASSERT ((unsigned) reg < pio->size);
396 if (pio->type == PCI_IO_MEM)
398 ret = ((uint8_t *) pio->addr.ptr)[reg];
400 else if (pio->type == PCI_IO_PORT)
402 ret = inb (pio->addr.port + reg);
405 PANIC ("pci: Invalid IO type\n");
411 pci_read_in (struct pci_io *pio UNUSED, int off UNUSED, size_t size UNUSED,
414 PANIC ("pci_read_in: STUB");
418 pci_write_out (struct pci_io *pio UNUSED, int off UNUSED, size_t size UNUSED,
419 const void *buf UNUSED)
421 PANIC ("pci_write_out: STUB");
425 pci_write_config (int bus, int dev, int func, int reg,
426 int size, uint32_t data)
430 config_offset = pci_config_offset (bus, dev, func, reg);
432 outl (PCI_REG_ADDR, config_offset);
437 outb (PCI_REG_DATA + (reg & 3), data);
441 outw (PCI_REG_DATA + (reg & 3), data);
445 outl (PCI_REG_DATA, data);
451 pci_read_config (int bus, int dev, int func, int reg, int size)
456 config_offset = pci_config_offset (bus, dev, func, reg);
458 outl (PCI_REG_ADDR, config_offset);
463 ret = inb (PCI_REG_DATA);
466 ret = inw (PCI_REG_DATA);
469 ret = inl (PCI_REG_DATA);
472 PANIC ("pci: Strange config read size\n");
478 /* read entire configuration header into memory */
480 pci_read_all_config (int bus, int dev, int func,
481 struct pci_config_header *pch)
484 for (i = 0; i < ((sizeof (struct pci_config_header) + 3) & ~3) / 4; i++)
486 ((uint32_t *) pch)[i] = pci_read_config (bus, dev, func, i * 4, 4);
491 /** scan PCI bus for all devices */
493 pci_scan_bus (int bus)
500 for (dev = 0; dev < PCI_MAX_DEV_PER_BUS; dev++)
502 struct pci_config_header pch;
505 pci_read_all_config (bus, dev, 0, &pch);
507 if (pch.pci_vendor_id == PCI_VENDOR_INVALID)
511 if (!(pch.pci_header & PCI_HEADER_MULTIFUNC))
516 for (func = 0; func < func_cnt; func++)
519 retbus = pci_probe (bus, dev, func, &pch);
520 if (retbus > max_bus)
528 /* get all information for a PCI device given bus/dev/func
529 add pci device to device list if applicable
530 return a new bus number if new bus is found
533 pci_probe (int bus, int dev, int func, struct pci_config_header *ph)
539 pci_read_all_config (bus, dev, func, ph);
540 if (ph->pci_vendor_id == PCI_VENDOR_INVALID)
544 pd = malloc (sizeof (struct pci_dev));
545 memcpy (&pd->pch, ph, sizeof (struct pci_config_header));
546 pd->irq_handler = NULL;
547 pd->irq_handler_aux = NULL;
552 list_init (&pd->io_ranges);
553 list_push_back (&devices, &pd->peer);
556 if (ph->pci_major == PCI_MAJOR_BRIDGE)
558 if (ph->pci_minor == PCI_MINOR_PCI)
559 return pci_pci_bridge (pd);
569 pci_setup_io (struct pci_dev *pd)
572 for (i = 0; i < PCI_BASE_COUNT; i++)
577 if (pd->pch.pci_base_reg[i] == 0)
582 /* determine io granularity.. */
583 pci_write_config (pd->bus, pd->dev, pd->func,
584 offsetof (struct pci_config_header, pci_base_reg[i]),
588 pci_read_config (pd->bus, pd->dev, pd->func,
589 offsetof (struct pci_config_header, pci_base_reg[i]),
592 /* configure BAR to the default */
593 pci_write_config (pd->bus, pd->dev, pd->func,
594 offsetof (struct pci_config_header, pci_base_reg[i]),
595 4, pd->pch.pci_base_reg[i]);
597 pio = malloc (sizeof (struct pci_io));
600 if (tmp & PCI_BASEADDR_IO)
602 pio->type = PCI_IO_PORT;
603 pio->size = (uint16_t) ((~tmp + 1) & 0xffff) + 1;
604 pio->addr.port = pd->pch.pci_base_reg[i] & ~1;
610 pio->type = PCI_IO_MEM;
611 pio->size = ROUND_UP ((~tmp + 1), PGSIZE);
612 ofs = (pd->pch.pci_base_reg[i] & 0xfffffff0 & PGMASK);
613 pio->addr.ptr = pci_alloc_mem ((void *) pd->pch.pci_base_reg[i],
615 if (pio->addr.ptr == NULL)
617 printf ("PCI: %d pages for %d:%d.%d failed - may not work\n",
618 pio->size / PGSIZE, pd->bus, pd->dev, pd->func);
624 pio->addr.ptr = (void *) ((uintptr_t) pio->addr.ptr + ofs);
628 /* add IO struct to device, if valid */
630 list_push_back (&pd->io_ranges, &pio->peer);
636 pci_power_on (struct pci_dev *pd UNUSED)
642 pci_pci_bridge (struct pci_dev *pd)
647 /* put bus into offline mode */
648 command = pd->pch.pci_command;
650 pci_write_config (pd->bus, pd->dev, pd->func,
651 offsetof (struct pci_config_header, pci_command),
653 pd->pch.pci_command = command;
655 /* set up primary bus */
656 pci_write_config (pd->bus, pd->dev, pd->func, 0x18, 1, pd->bus);
658 pci_write_config (pd->bus, pd->dev, pd->func, 0x19, 1, pd->bus + 1);
660 /* disable subordinates */
661 pci_write_config (pd->bus, pd->dev, pd->func, 0x1a, 1, 0xff);
663 /* scan this new bus */
664 max_bus = pci_scan_bus (pd->bus + 1);
666 /* set subordinate to the actual last bus */
667 pci_write_config (pd->bus, pd->dev, pd->func, 0x1a, 1, max_bus);
671 pci_write_config (pd->bus, pd->dev, pd->func,
672 offsetof (struct pci_config_header, pci_command),
674 pd->pch.pci_command = command;
679 /* alert all PCI devices waiting on interrupt line that IRQ fired */
681 pci_interrupt (struct intr_frame *frame)
686 int_line = frame->vec_no - 0x20;
687 e = list_begin (&int_devices);
688 while (e != list_end (&int_devices))
692 pd = list_entry (e, struct pci_dev, int_peer);
693 if (pd->pch.pci_int_line == int_line)
694 pd->irq_handler (pd->irq_handler_aux);
699 /* display information on all USB devices */
701 pci_print_stats (void)
705 e = list_begin (&devices);
706 while (e != list_end (&devices))
710 pd = list_entry (e, struct pci_dev, peer);
711 pci_print_dev_info (pd);
718 pci_print_dev_info (struct pci_dev *pd)
720 printf ("PCI Device %d:%d.%d (%x,%x): %s - %s (%s) IRQ %d\n",
721 pd->bus, pd->dev, pd->func,
722 pd->pch.pci_vendor_id,
723 pd->pch.pci_device_id,
724 pci_lookup_vendor (pd->pch.pci_vendor_id),
725 pci_lookup_device (pd->pch.pci_vendor_id, pd->pch.pci_device_id),
726 pci_lookup_class (pd->pch.pci_major, pd->pch.pci_minor,
727 pd->pch.pci_interface), pd->pch.pci_int_line);
731 pci_mask_irq (struct pci_dev *pd)
733 intr_irq_mask (pd->pch.pci_int_line);
737 pci_unmask_irq (struct pci_dev *pd)
739 intr_irq_unmask (pd->pch.pci_int_line);
743 pci_write_config16 (struct pci_dev *pd, int off, uint16_t data)
745 pci_write_config (pd->bus, pd->dev, pd->func, off, 2, data);
749 pci_write_config32 (struct pci_dev *pd, int off, uint32_t data)
751 pci_write_config (pd->bus, pd->dev, pd->func, off, 4, data);
755 pci_write_config8 (struct pci_dev *pd, int off, uint8_t data)
757 pci_write_config (pd->bus, pd->dev, pd->func, off, 1, data);
761 pci_read_config8 (struct pci_dev *pd, int off)
763 return pci_read_config (pd->bus, pd->dev, pd->func, off, 1);
767 pci_read_config16 (struct pci_dev * pd, int off)
769 return pci_read_config (pd->bus, pd->dev, pd->func, off, 2);
773 pci_read_config32 (struct pci_dev * pd, int off)
775 return pci_read_config (pd->bus, pd->dev, pd->func, off, 4);
779 /** allocate PCI memory pages for PCI devices */
781 pci_alloc_mem (void *phys_ptr, int pages)
786 phys_ptr = (void *) ((uintptr_t) phys_ptr & ~PGMASK);
788 /* not enough space to allocate? */
789 if ((unsigned) (num_pci_pages + pages) >= (unsigned) PCI_ADDR_ZONE_PAGES)
794 /* insert into PCI_ZONE */
795 for (i = 0; i < pages; i++)
797 uint32_t pte_idx = (num_pci_pages + i) % 1024;
798 uint32_t pde_idx = (num_pci_pages + i) / 1024;
802 pde_idx += pd_no ((void *) PCI_ADDR_ZONE_BEGIN);
803 pte = ((uint32_t) phys_ptr + (i * PGSIZE)) | PTE_P | PTE_W | PTE_CD;
804 pt = (uint32_t *) (ptov (init_page_dir[pde_idx] & ~PGMASK));
808 vaddr = (void *) (PCI_ADDR_ZONE_BEGIN + (num_pci_pages * PGSIZE));
809 num_pci_pages += pages;