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7 <TITLE>FreeVGA - VGA Display Generation</TITLE>
11 <CENTER><A HREF="../home.htm">Home</A> <A HREF="#intro">Intro</A> <A HREF="#clocks">Clocks</A>
12 <A HREF="#horiz">Horizontal</A> <A HREF="#vert">Vertical</A> <A HREF="#monitor">Monitoring</A>
13 <A HREF="#misc">Misc</A> <A HREF="vga.htm#general">Back</A>
14 <HR><B>Hardware Level VGA and SVGA Video Programming Information Page</B></CENTER>
16 <CENTER>VGA Display Generation
18 <A NAME="intro"></A><B>Introduction</B>
19 <BR> This page documents the
20 configuration of the VGA's CRTC registers which control the framing and
21 timing of video signals sent to the display device, usually a monitor.
23 <P><A NAME="clocks"></A><B>Dot Clocks</B>
24 <BR> The standard VGA has two
25 "standard" dot clock frequencies available to it, as well as a possible
26 "external" clock source, which is implementation dependent. The two
27 standard clock frequencies are nominally 25 Mhz and 28 MHz. Some
28 chipsets use 25.000 MHz and 28.000 MHz, while others use slightly greater
29 clock frequencies. The IBM VGA chipset I have uses 25.1750 MHz
30 Mhz and 28.3220 crystals. Some newer cards use the closest generated
31 frequency produced by their clock chip. In most circumstances the
32 IBM VGA timings can be assumed as the monitor should allow an amount of
33 variance; however, if you know the actual frequencies used you should use
34 them in your timing calculations.
35 <BR> The dot clock source in
36 the VGA hardware is selected using the <A HREF="extreg.htm#3CCR3C2W">Clock
37 Select</A> field. For the VGA, two of the values are undefined; some
38 SVGA chipsets use the undefined values for clock frequencies used for 132
39 column mode and such. The 25 MHz clock is designed for 320 and 640
40 pixel modes and the 28 MHz is designed for 360 and 720 pixel modes. The
41 <A HREF="seqreg.htm#01">Dot Clock Rate</A> field specifies whether to use
42 the dot clock source directly or to divide it in half before using it as
43 the actual dot clock rate.
45 <P><A NAME="horiz"></A><B>Horizontal Timing</B>
46 <BR> The VGA measures horizontal
47 timing periods in terms of character clocks, which can either be 8 or 9
48 dot clocks, as specified by the <A HREF="seqreg.htm#01">9/8 Dot Mode</A>
49 field. The 9 dot clock mode was included for monochrome emulation
50 and 9-dot wide character modes, and can be used to provide 360 and 720
51 pixel wide modes that work on all standard VGA monitors, when combined
52 with a 28 Mhz dot clock. The VGA uses a horizontal character counter which
53 is incremented at each character, which the horizontal timing circuitry
54 compares against the values of the horizontal timing fields to control
55 the horizontal state. The horizontal periods that are controlled are the
56 active display, overscan, blanking, and refresh periods.
57 <BR> The start of the active
58 display period coincides with the resetting of the horizontal character
59 counter, thus is fixed at zero. The value at which the horizontal
60 character is reset is controlled by the <A HREF="crtcreg.htm#00">Horizontal
61 Total</A> field. Note, however, that the value programmed into the <A HREF="crtcreg.htm#00">Horizontal
62 Total</A> field is actually 5 less than the actual value due to timing
64 <BR> The end of the active display
65 period is controlled by the <A HREF="crtcreg.htm#01">End Horizontal Display</A>
66 field. When the horizontal character counter is equal to the value
67 of this field, the sequencer begins outputting the color specified by the
68 <A HREF="attrreg.htm#11">Overscan Palette Index</A> field. This continues
69 until the active display begins at the beginning of the next scan line
70 when the active display begins again. Note that the horizontal blanking
71 takes precedence over the sequencer and attribute controller.
72 <BR> The horizontal blanking
73 period begins when the character clock equals the value of the <A HREF="crtcreg.htm#02">Start
74 Horizontal Blanking</A> field. During the horizontal blanking period,
75 the output voltages of the DAC signal the monitor to turn off the guns.
76 Under normal conditions, this prevents the overscan color from being displayed
77 during the horizontal retrace period. This period extends until the
78 lower 6 bits of the <A HREF="crtcreg.htm#03">End Horizontal Blanking</A>
79 field match the lower 6 bits of the horizontal character counter.
80 This allows for a blanking period from 1 to 64 character clocks, although
81 some implementations may treat 64 as 0 character clocks in length.
82 The blanking period may occur anywhere in the scan line, active display
83 or otherwise even though its meant to appear outside the active display
84 period. It takes precedence over all other VGA output. There
85 is also no requirement that blanking occur at all. If the <A HREF="crtcreg.htm#02">Start
86 Horizontal Blanking</A> field falls outside the maximum value of the character
87 clock determined by the <A HREF="crtcreg.htm#00">Horizontal Total</A> field,
88 then no blanking will occur at all. Note that due to the setting
89 of the <A HREF="crtcreg.htm#00">Horizontal Total</A> field, the first match
90 for the <A HREF="crtcreg.htm#03">End Horizontal Blanking</A> field may
91 be on the following scan line.
92 <BR> Similar to the horizontal
93 blanking period, the horizontal retrace period is specified by the <A HREF="crtcreg.htm#04">Start
94 Horizontal Retrace</A> and <A HREF="crtcreg.htm#05">End Horizontal Retrace</A>
95 fields. The horizontal retrace period begins when the character clock equals
96 the value stored in the <A HREF="crtcreg.htm#04">Start Horizontal Retrace</A>
97 field. The horizontal retrace ends when the lower 5 bits of the character
98 clock match the bit pattern stored in the <A HREF="crtcreg.htm#05">End
99 Horizontal Retrace</A> field, allowing a retrace period from 1 to 32 clocks;
100 however, a particular implementation may treat 32 clocks as zero clocks
101 in length. The operation of this is identical to that of the horizontal
102 blanking mechanism with the exception of being a 5 bit comparison instead
103 of 6, and affecting the horizontal retrace signal instead of the horizontal
105 <BR> There are two horizontal
106 timing fields that are described as being related to internal timings of
107 the VGA, the <A HREF="crtcreg.htm#03">Display Enable Skew</A> and <A HREF="crtcreg.htm#05">Horizontal
108 Retrace Skew</A> fields. In the VGA they do seem to affect the timing,
109 but also do not seem to be necessary for the operation of the VGA and are
110 pretty much unused. These registers were required by the IBM VGA
111 implementations, so I'm assuming this was added in the early stages of
112 the VGA design for EGA compatibility, but the internal timings were changed
113 to more friendly ones making the use of these fields unnecessary.
114 It seems to be totally safe to set these fields to 0 and ignore them.
115 See the register descriptions for more details, if you have to deal with
116 software that programs them.
118 <P><A NAME="vert"></A><B>Vertical Timing</B>
119 <BR> The VGA maintains a scanline
120 counter which is used to measure vertical timing periods. This counter
121 begins at zero which coincides with the first scan line of the active display.
122 This counter is set to zero before the beginning of the first scanline
123 of the active display. Depending on the setting of the <A HREF="crtcreg.htm#17">Divide
124 Scan Line Clock by 2</A> field, this counter is incremented either every
125 scanline, or every second scanline. The vertical scanline counter
126 is incremented before the beginning of each horizontal scan line, as all
127 of the VGA's vertical timing values are measured at the beginning of the
128 scan line, after the counter has ben set/incremented. The maximum
129 value of the scanline counter is specified by the <A HREF="crtcreg.htm#06">Vertical
130 Total</A> field. Note that, like the rest of the vertical timing
131 values that "overflow" an 8-bit register, the most significant bits are
132 located in the <A HREF="crtcreg.htm#07">Overflow Register</A>. The
133 <A HREF="crtcreg.htm#06">Vertical Total</A> field is programmed with the
134 value of the scanline counter at the beginning of the last scanline.
135 <BR> The vertical active display
136 period begins when the scanline counter is at zero, and extends up to the
137 value specified by the <A HREF="crtcreg.htm#12">Vertical Display End</A>
138 field. This field is set with the value of the scanline counter at
139 the beginning of the first inactive scanline, telling the video hardware
140 when to stop outputting scanlines of sequenced pixel data and outputs the
141 attribute specified by the <A HREF="attrreg.htm#11">Overscan Palette Index</A>
142 field in the horizontal active display period of those scanlines.
143 This continues until the start of the next frame when the active display
145 <BR> The <A HREF="crtcreg.htm#15">Start
146 Vertical Blanking</A> and <A HREF="crtcreg.htm#16">End Vertical Blanking</A>
147 fields control the vertical blanking interval. The <A HREF="crtcreg.htm#15">Start
148 Vertical Blanking</A> field is programmed with the value of the scanline
149 counter at the beginning of the scanline to begin blanking at. The
150 value of the <A HREF="crtcreg.htm#16">End Vertical Blanking</A> field is
151 set to the lower eight bits of the scanline counter at the beginning of
152 the scanline after the last scanline of vertical blanking.
153 <BR> The <A HREF="crtcreg.htm#10">Vertical
154 Retrace Start</A> and <A HREF="crtcreg.htm#11">Vertical Retrace End</A>
155 fields determine the length of the vertical retrace interval. The
156 <A HREF="crtcreg.htm#10">Vertical Retrace Start</A> field contains the
157 value of the scanline counter at the beginning of the first scanline where
158 the vertical retrace signal is asserted. The <A HREF="crtcreg.htm#11">Vertical
159 Retrace End</A> field is programmed with the value of the lower four bits
160 of the scanline counter at the beginning of the scanline after the last
161 scanline where the vertical retrace signal is asserted.
163 <P><A NAME="monitor"></A><B>Monitoring Timing</B>
164 <BR> There are certain operations
165 that should be performed during certain periods of the display cycle to
166 minimize visual artifacts, such as attribute and DAC writes. There
167 are two bit fields that return the current state of the VGA, the <A HREF="extreg.htm#3xAR">Display
168 Disabled</A> and <A HREF="extreg.htm#3xAR">Vertical Retrace</A> fields.
169 The <A HREF="extreg.htm#3xAR">Display Disabled</A> field is set to 1 when
170 the display enable signal is not asserted, providing the programmer with
171 a means to determine if the video hardware is currently refreshing the
172 active display or it is currently outputting blanking.
173 <BR> The <A HREF="extreg.htm#3xAR">Vertical
174 Retrace</A> field signals whether or not the VGA is in a vertical retrace
175 period. This is useful for determining the end of a display period,
176 which can be used by applications that need to update the display every
177 period such as when doing animation. Under normal conditions, when
178 the blanking signal is asserted during the entire vertical retrace, this
179 can also be used to detect this period of blanking, such that a large amount
180 of register accesses can be performed, such as reloading the complete set
183 <P><A NAME="misc"></A><B>Miscellaneous</B>
184 <BR> There are a few registers
185 that affect display generation, but don't fit neatly into the horizontal
186 or vertical timing categories. The first is the <A HREF="crtcreg.htm#17">Sync
187 Enable</A> field which controls whether the horizontal and vertical sync
188 signals are sent to the display or masked off. The sync signals should
189 be disabled while setting up a new mode to ensure that an improper signal
190 that could damage the display is not being output. Keeping the sync
191 disabled for a period of one or more frames helps the display determine
192 that a mode change has occurred as well.
193 <BR> The <A HREF="crtcreg.htm#11">Memory Refresh Bandwidth</A>
194 field is used by the original IBM VGA hardware and some compatible VGA/SVGA
195 chipsets to control how often the display memory is refreshed. This
196 field controls whether the VGA hardware provides 3 or 5 memory refresh
197 cycles per scanline. At or above VGA horizontal refresh rates, this
198 field should be programmed for 3 memory refresh cycles per scanline.
199 Below this rate, for compatibility's sake the 5 memory refresh cycles per
200 scanline setting might be safer, see the <A HREF="crtcreg.htm#11">Memory
201 Refresh Bandwidth</A> field for (slightly) more information.
204 <BR>Notice: All trademarks used or referred to on this page are the property
205 of their respective owners.
206 <BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
207 noted. Permission for utilization and distribution is subject to the terms
208 of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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