1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
3 Copyright (C) 1991, 1992, 1993, 1994, 1996 Free Software Foundation, Inc.
5 This file is free software; you can redistribute it and/or modify
6 it under the terms of the GNU Library General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or (at your
8 option) any later version.
10 This file is distributed in the hope that it will be useful, but
11 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public
13 License for more details.
15 You should have received a copy of the GNU Library General Public License
16 along with this file; see the file COPYING.LIB. If not, write to
17 the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 MA 02111-1307, USA. */
20 #define LONGLONG_STANDALONE 1 /* blp 1998/10/29 */
22 /* You have to define the following before including this file:
24 UWtype -- An unsigned type, default type for operations (typically a "word")
25 UHWtype -- An unsigned type, at least half the size of UWtype.
26 UDWtype -- An unsigned type, at least twice as large a UWtype
27 W_TYPE_SIZE -- size in bits of UWtype
29 SItype, USItype -- Signed and unsigned 32 bit types.
30 DItype, UDItype -- Signed and unsigned 64 bit types.
32 On a 32 bit machine UWtype should typically be USItype;
33 on a 64 bit machine, UWtype should typically be UDItype.
36 #define __BITS4 (W_TYPE_SIZE / 4)
37 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
38 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
39 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
41 /* This is used to make sure no undesirable sharing between different libraries
42 that use this file takes place. */
44 #define __MPN(x) __##x
47 /* Define auxiliary asm macros.
49 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
50 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
51 word product in HIGH_PROD and LOW_PROD.
53 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
54 UDWtype product. This is just a variant of umul_ppmm.
56 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
57 denominator) divides a UDWtype, composed by the UWtype integers
58 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
59 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
60 than DENOMINATOR for correct operation. If, in addition, the most
61 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
62 UDIV_NEEDS_NORMALIZATION is defined to 1.
64 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
65 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
68 5) count_leading_zeros(count, x) counts the number of zero-bits from the
69 msb to the first non-zero bit in the UWtype X. This is the number of
70 steps X needs to be shifted left to set the msb. Undefined for X == 0,
71 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
73 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
74 from the least significant end.
76 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
77 high_addend_2, low_addend_2) adds two UWtype integers, composed by
78 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
79 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
80 (i.e. carry out) is not stored anywhere, and is lost.
82 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
83 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
84 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
85 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
86 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
89 If any of these macros are left undefined for a particular CPU,
92 /* The CPUs come in alphabetical order below.
94 Please add support for more CPUs here, or improve the current support
95 for the CPUs below! */
97 #if defined (__CHECKER__)
101 #if defined (__GNUC__) && !defined (NO_ASM)
103 /* We sometimes need to clobber "cc" with gcc2, but that would not be
104 understood by gcc1. Use cpp to avoid major code duplication. */
107 #define __AND_CLOBBER_CC
108 #else /* __GNUC__ >= 2 */
109 #define __CLOBBER_CC : "cc"
110 #define __AND_CLOBBER_CC , "cc"
111 #endif /* __GNUC__ < 2 */
113 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
114 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
115 __asm__ ("add %1,%4,%5
117 : "=r" ((USItype)(sh)), \
118 "=&r" ((USItype)(sl)) \
119 : "%r" ((USItype)(ah)), \
120 "rI" ((USItype)(bh)), \
121 "%r" ((USItype)(al)), \
122 "rI" ((USItype)(bl)))
123 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
124 __asm__ ("sub %1,%4,%5
126 : "=r" ((USItype)(sh)), \
127 "=&r" ((USItype)(sl)) \
128 : "r" ((USItype)(ah)), \
129 "rI" ((USItype)(bh)), \
130 "r" ((USItype)(al)), \
131 "rI" ((USItype)(bl)))
132 #define umul_ppmm(xh, xl, m0, m1) \
134 USItype __m0 = (m0), __m1 = (m1); \
135 __asm__ ("multiplu %0,%1,%2" \
136 : "=r" ((USItype)(xl)) \
139 __asm__ ("multmu %0,%1,%2" \
140 : "=r" ((USItype)(xh)) \
144 #define udiv_qrnnd(q, r, n1, n0, d) \
145 __asm__ ("dividu %0,%3,%4" \
146 : "=r" ((USItype)(q)), \
147 "=q" ((USItype)(r)) \
148 : "1" ((USItype)(n1)), \
149 "r" ((USItype)(n0)), \
151 #define count_leading_zeros(count, x) \
152 __asm__ ("clz %0,%1" \
153 : "=r" ((USItype)(count)) \
154 : "r" ((USItype)(x)))
155 #define COUNT_LEADING_ZEROS_0 32
156 #endif /* __a29k__ */
158 #if defined (__alpha) && W_TYPE_SIZE == 64
159 #define umul_ppmm(ph, pl, m0, m1) \
161 UDItype __m0 = (m0), __m1 = (m1); \
162 __asm__ ("umulh %r1,%2,%0" \
163 : "=r" ((UDItype) ph) \
166 (pl) = __m0 * __m1; \
169 #ifndef LONGLONG_STANDALONE
170 #define udiv_qrnnd(q, r, n1, n0, d) \
172 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
175 extern UDItype __udiv_qrnnd ();
176 #define UDIV_TIME 220
177 #endif /* LONGLONG_STANDALONE */
180 #if defined (__arm__) && W_TYPE_SIZE == 32
181 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
182 __asm__ ("adds %1, %4, %5
184 : "=r" ((USItype)(sh)), \
185 "=&r" ((USItype)(sl)) \
186 : "%r" ((USItype)(ah)), \
187 "rI" ((USItype)(bh)), \
188 "%r" ((USItype)(al)), \
189 "rI" ((USItype)(bl)))
190 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
191 __asm__ ("subs %1, %4, %5
193 : "=r" ((USItype)(sh)), \
194 "=&r" ((USItype)(sl)) \
195 : "r" ((USItype)(ah)), \
196 "rI" ((USItype)(bh)), \
197 "r" ((USItype)(al)), \
198 "rI" ((USItype)(bl)))
199 #define umul_ppmm(xh, xl, a, b) \
200 __asm__ ("%@ Inlined umul_ppmm
201 mov %|r0, %2, lsr #16
202 mov %|r2, %3, lsr #16
203 bic %|r1, %2, %|r0, lsl #16
204 bic %|r2, %3, %|r2, lsl #16
209 adds %|r1, %|r2, %|r1
211 adds %1, %1, %|r1, lsl #16
212 adc %0, %0, %|r1, lsr #16" \
213 : "=&r" ((USItype)(xh)), \
214 "=r" ((USItype)(xl)) \
215 : "r" ((USItype)(a)), \
219 #define UDIV_TIME 100
222 #if defined (__clipper__) && W_TYPE_SIZE == 32
223 #define umul_ppmm(w1, w0, u, v) \
224 ({union {UDItype __ll; \
225 struct {USItype __l, __h;} __i; \
227 __asm__ ("mulwux %2,%0" \
229 : "%0" ((USItype)(u)), \
230 "r" ((USItype)(v))); \
231 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
232 #define smul_ppmm(w1, w0, u, v) \
233 ({union {DItype __ll; \
234 struct {SItype __l, __h;} __i; \
236 __asm__ ("mulwx %2,%0" \
238 : "%0" ((SItype)(u)), \
239 "r" ((SItype)(v))); \
240 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
241 #define __umulsidi3(u, v) \
243 __asm__ ("mulwux %2,%0" \
245 : "%0" ((USItype)(u)), \
246 "r" ((USItype)(v))); \
248 #endif /* __clipper__ */
250 #if defined (__gmicro__) && W_TYPE_SIZE == 32
251 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
252 __asm__ ("add.w %5,%1
254 : "=g" ((USItype)(sh)), \
255 "=&g" ((USItype)(sl)) \
256 : "%0" ((USItype)(ah)), \
257 "g" ((USItype)(bh)), \
258 "%1" ((USItype)(al)), \
260 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
261 __asm__ ("sub.w %5,%1
263 : "=g" ((USItype)(sh)), \
264 "=&g" ((USItype)(sl)) \
265 : "0" ((USItype)(ah)), \
266 "g" ((USItype)(bh)), \
267 "1" ((USItype)(al)), \
269 #define umul_ppmm(ph, pl, m0, m1) \
270 __asm__ ("mulx %3,%0,%1" \
271 : "=g" ((USItype)(ph)), \
272 "=r" ((USItype)(pl)) \
273 : "%0" ((USItype)(m0)), \
275 #define udiv_qrnnd(q, r, nh, nl, d) \
276 __asm__ ("divx %4,%0,%1" \
277 : "=g" ((USItype)(q)), \
278 "=r" ((USItype)(r)) \
279 : "1" ((USItype)(nh)), \
280 "0" ((USItype)(nl)), \
282 #define count_leading_zeros(count, x) \
283 __asm__ ("bsch/1 %1,%0" \
285 : "g" ((USItype)(x)), \
289 #if defined (__hppa) && W_TYPE_SIZE == 32
290 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
291 __asm__ ("add %4,%5,%1
293 : "=r" ((USItype)(sh)), \
294 "=&r" ((USItype)(sl)) \
295 : "%rM" ((USItype)(ah)), \
296 "rM" ((USItype)(bh)), \
297 "%rM" ((USItype)(al)), \
298 "rM" ((USItype)(bl)))
299 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
300 __asm__ ("sub %4,%5,%1
302 : "=r" ((USItype)(sh)), \
303 "=&r" ((USItype)(sl)) \
304 : "rM" ((USItype)(ah)), \
305 "rM" ((USItype)(bh)), \
306 "rM" ((USItype)(al)), \
307 "rM" ((USItype)(bl)))
308 #if defined (_PA_RISC1_1)
309 #define umul_ppmm(wh, wl, u, v) \
311 union {UDItype __ll; \
312 struct {USItype __h, __l;} __i; \
314 __asm__ ("xmpyu %1,%2,%0" \
315 : "=*f" (__xx.__ll) \
316 : "*f" ((USItype)(u)), \
317 "*f" ((USItype)(v))); \
318 (wh) = __xx.__i.__h; \
319 (wl) = __xx.__i.__l; \
327 #ifndef LONGLONG_STANDALONE
328 #define udiv_qrnnd(q, r, n1, n0, d) \
330 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
333 extern USItype __udiv_qrnnd ();
334 #endif /* LONGLONG_STANDALONE */
335 #define count_leading_zeros(count, x) \
340 extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
341 extru,tr %1,15,16,%1 ; No. Shift down, skip add.
342 ldo 16(%0),%0 ; Yes. Perform add.
343 extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
344 extru,tr %1,23,8,%1 ; No. Shift down, skip add.
345 ldo 8(%0),%0 ; Yes. Perform add.
346 extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
347 extru,tr %1,27,4,%1 ; No. Shift down, skip add.
348 ldo 4(%0),%0 ; Yes. Perform add.
349 extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
350 extru,tr %1,29,2,%1 ; No. Shift down, skip add.
351 ldo 2(%0),%0 ; Yes. Perform add.
352 extru %1,30,1,%1 ; Extract bit 1.
353 sub %0,%1,%0 ; Subtract it.
354 " : "=r" (count), "=r" (__tmp) : "1" (x)); \
358 #if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32
359 #define umul_ppmm(xh, xl, m0, m1) \
361 union {UDItype __ll; \
362 struct {USItype __h, __l;} __i; \
364 USItype __m0 = (m0), __m1 = (m1); \
365 __asm__ ("mr %0,%3" \
366 : "=r" (__xx.__i.__h), \
367 "=r" (__xx.__i.__l) \
370 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
371 (xh) += ((((SItype) __m0 >> 31) & __m1) \
372 + (((SItype) __m1 >> 31) & __m0)); \
374 #define smul_ppmm(xh, xl, m0, m1) \
376 union {DItype __ll; \
377 struct {USItype __h, __l;} __i; \
379 __asm__ ("mr %0,%3" \
380 : "=r" (__xx.__i.__h), \
381 "=r" (__xx.__i.__l) \
384 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
386 #define sdiv_qrnnd(q, r, n1, n0, d) \
388 union {DItype __ll; \
389 struct {USItype __h, __l;} __i; \
391 __xx.__i.__h = n1; __xx.__i.__l = n0; \
392 __asm__ ("dr %0,%2" \
394 : "0" (__xx.__ll), "r" (d)); \
395 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
399 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
400 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
403 : "=r" ((USItype)(sh)), \
404 "=&r" ((USItype)(sl)) \
405 : "%0" ((USItype)(ah)), \
406 "g" ((USItype)(bh)), \
407 "%1" ((USItype)(al)), \
409 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
412 : "=r" ((USItype)(sh)), \
413 "=&r" ((USItype)(sl)) \
414 : "0" ((USItype)(ah)), \
415 "g" ((USItype)(bh)), \
416 "1" ((USItype)(al)), \
418 #define umul_ppmm(w1, w0, u, v) \
420 : "=a" ((USItype)(w0)), \
421 "=d" ((USItype)(w1)) \
422 : "%0" ((USItype)(u)), \
424 #define udiv_qrnnd(q, r, n1, n0, d) \
426 : "=a" ((USItype)(q)), \
427 "=d" ((USItype)(r)) \
428 : "0" ((USItype)(n0)), \
429 "1" ((USItype)(n1)), \
431 #define count_leading_zeros(count, x) \
434 __asm__ ("bsrl %1,%0" \
435 : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
436 (count) = __cbtmp ^ 31; \
438 #define count_trailing_zeros(count, x) \
439 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
448 #if defined (__i860__) && W_TYPE_SIZE == 32
449 #define rshift_rhlc(r,h,l,c) \
450 __asm__ ("shr %3,r0,r0\;shrd %1,%2,%0" \
451 "=r" (r) : "r" (h), "r" (l), "rn" (c))
454 #if defined (__i960__) && W_TYPE_SIZE == 32
455 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
456 __asm__ ("cmpo 1,0\;addc %5,%4,%1\;addc %3,%2,%0" \
457 : "=r" ((USItype)(sh)), \
458 "=&r" ((USItype)(sl)) \
459 : "%dI" ((USItype)(ah)), \
460 "dI" ((USItype)(bh)), \
461 "%dI" ((USItype)(al)), \
462 "dI" ((USItype)(bl)))
463 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
464 __asm__ ("cmpo 0,0\;subc %5,%4,%1\;subc %3,%2,%0" \
465 : "=r" ((USItype)(sh)), \
466 "=&r" ((USItype)(sl)) \
467 : "dI" ((USItype)(ah)), \
468 "dI" ((USItype)(bh)), \
469 "dI" ((USItype)(al)), \
470 "dI" ((USItype)(bl)))
471 #define umul_ppmm(w1, w0, u, v) \
472 ({union {UDItype __ll; \
473 struct {USItype __l, __h;} __i; \
475 __asm__ ("emul %2,%1,%0" \
477 : "%dI" ((USItype)(u)), \
478 "dI" ((USItype)(v))); \
479 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
480 #define __umulsidi3(u, v) \
482 __asm__ ("emul %2,%1,%0" \
484 : "%dI" ((USItype)(u)), \
485 "dI" ((USItype)(v))); \
487 #define udiv_qrnnd(q, r, nh, nl, d) \
489 union {UDItype __ll; \
490 struct {USItype __l, __h;} __i; \
492 __nn.__i.__h = (nh); __nn.__i.__l = (nl); \
493 __asm__ ("ediv %d,%n,%0" \
495 : "dI" (__nn.__ll), \
496 "dI" ((USItype)(d))); \
497 (r) = __rq.__i.__l; (q) = __rq.__i.__h; \
499 #define count_leading_zeros(count, x) \
502 __asm__ ("scanbit %1,%0" \
504 : "r" ((USItype)(x))); \
505 (count) = __cbtmp ^ 31; \
507 #define COUNT_LEADING_ZEROS_0 (-32) /* sic */
508 #if defined (__i960mx) /* what is the proper symbol to test??? */
509 #define rshift_rhlc(r,h,l,c) \
511 union {UDItype __ll; \
512 struct {USItype __l, __h;} __i; \
514 __nn.__i.__h = (h); __nn.__i.__l = (l); \
515 __asm__ ("shre %2,%1,%0" \
516 : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \
521 #if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
522 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
523 __asm__ ("add%.l %5,%1
525 : "=d" ((USItype)(sh)), \
526 "=&d" ((USItype)(sl)) \
527 : "%0" ((USItype)(ah)), \
528 "d" ((USItype)(bh)), \
529 "%1" ((USItype)(al)), \
531 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
532 __asm__ ("sub%.l %5,%1
534 : "=d" ((USItype)(sh)), \
535 "=&d" ((USItype)(sl)) \
536 : "0" ((USItype)(ah)), \
537 "d" ((USItype)(bh)), \
538 "1" ((USItype)(al)), \
540 #if (defined (__mc68020__) || defined (__NeXT__) || defined(mc68020))
541 #define umul_ppmm(w1, w0, u, v) \
542 __asm__ ("mulu%.l %3,%1:%0" \
543 : "=d" ((USItype)(w0)), \
544 "=d" ((USItype)(w1)) \
545 : "%0" ((USItype)(u)), \
546 "dmi" ((USItype)(v)))
548 #define udiv_qrnnd(q, r, n1, n0, d) \
549 __asm__ ("divu%.l %4,%1:%0" \
550 : "=d" ((USItype)(q)), \
551 "=d" ((USItype)(r)) \
552 : "0" ((USItype)(n0)), \
553 "1" ((USItype)(n1)), \
554 "dmi" ((USItype)(d)))
556 #define sdiv_qrnnd(q, r, n1, n0, d) \
557 __asm__ ("divs%.l %4,%1:%0" \
558 : "=d" ((USItype)(q)), \
559 "=d" ((USItype)(r)) \
560 : "0" ((USItype)(n0)), \
561 "1" ((USItype)(n1)), \
562 "dmi" ((USItype)(d)))
563 #define count_leading_zeros(count, x) \
564 __asm__ ("bfffo %1{%b2:%b2},%0" \
565 : "=d" ((USItype)(count)) \
566 : "od" ((USItype)(x)), "n" (0))
567 #define COUNT_LEADING_ZEROS_0 32
568 #else /* not mc68020 */
569 #define umul_ppmm(xh, xl, a, b) \
570 do { USItype __umul_tmp1, __umul_tmp2; \
571 __asm__ ("| Inlined umul_ppmm
592 | End inlined umul_ppmm" \
593 : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
594 "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
595 : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
597 #define UMUL_TIME 100
598 #define UDIV_TIME 400
599 #endif /* not mc68020 */
602 #if defined (__m88000__) && W_TYPE_SIZE == 32
603 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
604 __asm__ ("addu.co %1,%r4,%r5
605 addu.ci %0,%r2,%r3" \
606 : "=r" ((USItype)(sh)), \
607 "=&r" ((USItype)(sl)) \
608 : "%rJ" ((USItype)(ah)), \
609 "rJ" ((USItype)(bh)), \
610 "%rJ" ((USItype)(al)), \
611 "rJ" ((USItype)(bl)))
612 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
613 __asm__ ("subu.co %1,%r4,%r5
614 subu.ci %0,%r2,%r3" \
615 : "=r" ((USItype)(sh)), \
616 "=&r" ((USItype)(sl)) \
617 : "rJ" ((USItype)(ah)), \
618 "rJ" ((USItype)(bh)), \
619 "rJ" ((USItype)(al)), \
620 "rJ" ((USItype)(bl)))
621 #define count_leading_zeros(count, x) \
624 __asm__ ("ff1 %0,%1" \
626 : "r" ((USItype)(x))); \
627 (count) = __cbtmp ^ 31; \
629 #define COUNT_LEADING_ZEROS_0 63 /* sic */
630 #if defined (__m88110__)
631 #define umul_ppmm(wh, wl, u, v) \
633 union {UDItype __ll; \
634 struct {USItype __h, __l;} __i; \
636 __asm__ ("mulu.d %0,%1,%2" \
638 : "r" ((USItype)(u)), \
639 "r" ((USItype)(v))); \
640 (wh) = __xx.__i.__h; \
641 (wl) = __xx.__i.__l; \
643 #define udiv_qrnnd(q, r, n1, n0, d) \
644 ({union {UDItype __ll; \
645 struct {USItype __h, __l;} __i; \
648 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
649 __asm__ ("divu.d %0,%1,%2" \
652 "r" ((USItype)(d))); \
653 (r) = (n0) - __q * (d); (q) = __q; })
658 #define UDIV_TIME 150
659 #endif /* __m88110__ */
660 #endif /* __m88000__ */
662 #if defined (__mips__) && W_TYPE_SIZE == 32
663 #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
664 #define umul_ppmm(w1, w0, u, v) \
665 __asm__ ("multu %2,%3" \
666 : "=l" ((USItype)(w0)), \
667 "=h" ((USItype)(w1)) \
668 : "d" ((USItype)(u)), \
671 #define umul_ppmm(w1, w0, u, v) \
672 __asm__ ("multu %2,%3
675 : "=d" ((USItype)(w0)), \
676 "=d" ((USItype)(w1)) \
677 : "d" ((USItype)(u)), \
681 #define UDIV_TIME 100
682 #endif /* __mips__ */
684 #if (defined (__mips) && __mips >= 3) && W_TYPE_SIZE == 64
685 #if __GNUC__ > 2 || __GNUC_MINOR__ >= 7
686 #define umul_ppmm(w1, w0, u, v) \
687 __asm__ ("dmultu %2,%3" \
688 : "=l" ((UDItype)(w0)), \
689 "=h" ((UDItype)(w1)) \
690 : "d" ((UDItype)(u)), \
693 #define umul_ppmm(w1, w0, u, v) \
694 __asm__ ("dmultu %2,%3
697 : "=d" ((UDItype)(w0)), \
698 "=d" ((UDItype)(w1)) \
699 : "d" ((UDItype)(u)), \
703 #define UDIV_TIME 140
704 #endif /* __mips__ */
706 #if defined (__ns32000__) && W_TYPE_SIZE == 32
707 #define umul_ppmm(w1, w0, u, v) \
708 ({union {UDItype __ll; \
709 struct {USItype __l, __h;} __i; \
711 __asm__ ("meid %2,%0" \
713 : "%0" ((USItype)(u)), \
714 "g" ((USItype)(v))); \
715 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
716 #define __umulsidi3(u, v) \
718 __asm__ ("meid %2,%0" \
720 : "%0" ((USItype)(u)), \
721 "g" ((USItype)(v))); \
723 #define udiv_qrnnd(q, r, n1, n0, d) \
724 ({union {UDItype __ll; \
725 struct {USItype __l, __h;} __i; \
727 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
728 __asm__ ("deid %2,%0" \
731 "g" ((USItype)(d))); \
732 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
733 #define count_trailing_zeros(count,x) \
735 __asm__ ("ffsd %2,%0" \
736 : "=r" ((USItype) (count)) \
737 : "0" ((USItype) 0), \
738 "r" ((USItype) (x))); \
740 #endif /* __ns32000__ */
742 #if (defined (_ARCH_PPC) || defined (_IBMR2)) && W_TYPE_SIZE == 32
743 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
745 if (__builtin_constant_p (bh) && (bh) == 0) \
746 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
747 : "=r" ((USItype)(sh)), \
748 "=&r" ((USItype)(sl)) \
749 : "%r" ((USItype)(ah)), \
750 "%r" ((USItype)(al)), \
751 "rI" ((USItype)(bl))); \
752 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
753 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
754 : "=r" ((USItype)(sh)), \
755 "=&r" ((USItype)(sl)) \
756 : "%r" ((USItype)(ah)), \
757 "%r" ((USItype)(al)), \
758 "rI" ((USItype)(bl))); \
760 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
761 : "=r" ((USItype)(sh)), \
762 "=&r" ((USItype)(sl)) \
763 : "%r" ((USItype)(ah)), \
764 "r" ((USItype)(bh)), \
765 "%r" ((USItype)(al)), \
766 "rI" ((USItype)(bl))); \
768 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
770 if (__builtin_constant_p (ah) && (ah) == 0) \
771 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
772 : "=r" ((USItype)(sh)), \
773 "=&r" ((USItype)(sl)) \
774 : "r" ((USItype)(bh)), \
775 "rI" ((USItype)(al)), \
776 "r" ((USItype)(bl))); \
777 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
778 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
779 : "=r" ((USItype)(sh)), \
780 "=&r" ((USItype)(sl)) \
781 : "r" ((USItype)(bh)), \
782 "rI" ((USItype)(al)), \
783 "r" ((USItype)(bl))); \
784 else if (__builtin_constant_p (bh) && (bh) == 0) \
785 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
786 : "=r" ((USItype)(sh)), \
787 "=&r" ((USItype)(sl)) \
788 : "r" ((USItype)(ah)), \
789 "rI" ((USItype)(al)), \
790 "r" ((USItype)(bl))); \
791 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
792 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
793 : "=r" ((USItype)(sh)), \
794 "=&r" ((USItype)(sl)) \
795 : "r" ((USItype)(ah)), \
796 "rI" ((USItype)(al)), \
797 "r" ((USItype)(bl))); \
799 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
800 : "=r" ((USItype)(sh)), \
801 "=&r" ((USItype)(sl)) \
802 : "r" ((USItype)(ah)), \
803 "r" ((USItype)(bh)), \
804 "rI" ((USItype)(al)), \
805 "r" ((USItype)(bl))); \
807 #define count_leading_zeros(count, x) \
808 __asm__ ("{cntlz|cntlzw} %0,%1" \
809 : "=r" ((USItype)(count)) \
810 : "r" ((USItype)(x)))
811 #define COUNT_LEADING_ZEROS_0 32
812 #if defined (_ARCH_PPC)
813 #define umul_ppmm(ph, pl, m0, m1) \
815 USItype __m0 = (m0), __m1 = (m1); \
816 __asm__ ("mulhwu %0,%1,%2" \
817 : "=r" ((USItype) ph) \
820 (pl) = __m0 * __m1; \
823 #define smul_ppmm(ph, pl, m0, m1) \
825 SItype __m0 = (m0), __m1 = (m1); \
826 __asm__ ("mulhw %0,%1,%2" \
827 : "=r" ((SItype) ph) \
830 (pl) = __m0 * __m1; \
833 #define UDIV_TIME 120
835 #define umul_ppmm(xh, xl, m0, m1) \
837 USItype __m0 = (m0), __m1 = (m1); \
838 __asm__ ("mul %0,%2,%3" \
839 : "=r" ((USItype)(xh)), \
840 "=q" ((USItype)(xl)) \
843 (xh) += ((((SItype) __m0 >> 31) & __m1) \
844 + (((SItype) __m1 >> 31) & __m0)); \
847 #define smul_ppmm(xh, xl, m0, m1) \
848 __asm__ ("mul %0,%2,%3" \
849 : "=r" ((SItype)(xh)), \
850 "=q" ((SItype)(xl)) \
854 #define sdiv_qrnnd(q, r, nh, nl, d) \
855 __asm__ ("div %0,%2,%4" \
856 : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
857 : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
858 #define UDIV_TIME 100
860 #endif /* Power architecture variants. */
862 #if defined (__pyr__) && W_TYPE_SIZE == 32
863 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
866 : "=r" ((USItype)(sh)), \
867 "=&r" ((USItype)(sl)) \
868 : "%0" ((USItype)(ah)), \
869 "g" ((USItype)(bh)), \
870 "%1" ((USItype)(al)), \
872 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
875 : "=r" ((USItype)(sh)), \
876 "=&r" ((USItype)(sl)) \
877 : "0" ((USItype)(ah)), \
878 "g" ((USItype)(bh)), \
879 "1" ((USItype)(al)), \
881 /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
882 #define umul_ppmm(w1, w0, u, v) \
883 ({union {UDItype __ll; \
884 struct {USItype __h, __l;} __i; \
886 __asm__ ("movw %1,%R0
888 : "=&r" (__xx.__ll) \
889 : "g" ((USItype) (u)), \
890 "g" ((USItype)(v))); \
891 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
894 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
895 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
898 : "=r" ((USItype)(sh)), \
899 "=&r" ((USItype)(sl)) \
900 : "%0" ((USItype)(ah)), \
901 "r" ((USItype)(bh)), \
902 "%1" ((USItype)(al)), \
904 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
907 : "=r" ((USItype)(sh)), \
908 "=&r" ((USItype)(sl)) \
909 : "0" ((USItype)(ah)), \
910 "r" ((USItype)(bh)), \
911 "1" ((USItype)(al)), \
913 #define umul_ppmm(ph, pl, m0, m1) \
915 USItype __m0 = (m0), __m1 = (m1); \
937 : "=r" ((USItype)(ph)), \
938 "=r" ((USItype)(pl)) \
942 (ph) += ((((SItype) __m0 >> 31) & __m1) \
943 + (((SItype) __m1 >> 31) & __m0)); \
946 #define UDIV_TIME 200
947 #define count_leading_zeros(count, x) \
949 if ((x) >= 0x10000) \
950 __asm__ ("clz %0,%1" \
951 : "=r" ((USItype)(count)) \
952 : "r" ((USItype)(x) >> 16)); \
955 __asm__ ("clz %0,%1" \
956 : "=r" ((USItype)(count)) \
957 : "r" ((USItype)(x))); \
963 #if defined (__sh2__) && W_TYPE_SIZE == 32
964 #define umul_ppmm(w1, w0, u, v) \
969 : "=r" ((USItype)(w1)), \
970 "=r" ((USItype)(w0)) \
971 : "r" ((USItype)(u)), \
977 #if defined (__sparc__) && W_TYPE_SIZE == 32
978 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
979 __asm__ ("addcc %r4,%5,%1
981 : "=r" ((USItype)(sh)), \
982 "=&r" ((USItype)(sl)) \
983 : "%rJ" ((USItype)(ah)), \
984 "rI" ((USItype)(bh)), \
985 "%rJ" ((USItype)(al)), \
986 "rI" ((USItype)(bl)) \
988 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
989 __asm__ ("subcc %r4,%5,%1
991 : "=r" ((USItype)(sh)), \
992 "=&r" ((USItype)(sl)) \
993 : "rJ" ((USItype)(ah)), \
994 "rI" ((USItype)(bh)), \
995 "rJ" ((USItype)(al)), \
996 "rI" ((USItype)(bl)) \
998 #if defined (__sparc_v8__)
999 /* Don't match immediate range because, 1) it is not often useful,
1000 2) the 'I' flag thinks of the range as a 13 bit signed interval,
1001 while we want to match a 13 bit interval, sign extended to 32 bits,
1002 but INTERPRETED AS UNSIGNED. */
1003 #define umul_ppmm(w1, w0, u, v) \
1004 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1005 : "=r" ((USItype)(w1)), \
1006 "=r" ((USItype)(w0)) \
1007 : "r" ((USItype)(u)), \
1010 #ifndef SUPERSPARC /* SuperSPARC's udiv only handles 53 bit dividends */
1011 #define udiv_qrnnd(q, r, n1, n0, d) \
1014 __asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
1015 : "=r" ((USItype)(__q)) \
1016 : "r" ((USItype)(n1)), \
1017 "r" ((USItype)(n0)), \
1018 "r" ((USItype)(d))); \
1019 (r) = (n0) - __q * (d); \
1022 #define UDIV_TIME 25
1023 #endif /* SUPERSPARC */
1024 #else /* ! __sparc_v8__ */
1025 #if defined (__sparclite__)
1026 /* This has hardware multiply but not divide. It also has two additional
1027 instructions scan (ffs from high bit) and divscc. */
1028 #define umul_ppmm(w1, w0, u, v) \
1029 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1030 : "=r" ((USItype)(w1)), \
1031 "=r" ((USItype)(w0)) \
1032 : "r" ((USItype)(u)), \
1035 #define udiv_qrnnd(q, r, n1, n0, d) \
1036 __asm__ ("! Inlined udiv_qrnnd
1037 wr %%g0,%2,%%y ! Not a delayed write for sparclite
1074 1: ! End of inline udiv_qrnnd" \
1075 : "=r" ((USItype)(q)), \
1076 "=r" ((USItype)(r)) \
1077 : "r" ((USItype)(n1)), \
1078 "r" ((USItype)(n0)), \
1079 "rI" ((USItype)(d)) \
1080 : "%g1" __AND_CLOBBER_CC)
1081 #define UDIV_TIME 37
1082 #define count_leading_zeros(count, x) \
1083 __asm__ ("scan %1,0,%0" \
1084 : "=r" ((USItype)(x)) \
1085 : "r" ((USItype)(count)))
1086 /* Early sparclites return 63 for an argument of 0, but they warn that future
1087 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1089 #endif /* __sparclite__ */
1090 #endif /* __sparc_v8__ */
1091 /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
1093 #define umul_ppmm(w1, w0, u, v) \
1094 __asm__ ("! Inlined umul_ppmm
1095 wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
1096 sra %3,31,%%g2 ! Don't move this insn
1097 and %2,%%g2,%%g2 ! Don't move this insn
1098 andcc %%g0,0,%%g1 ! Don't move this insn
1134 : "=r" ((USItype)(w1)), \
1135 "=r" ((USItype)(w0)) \
1136 : "%rI" ((USItype)(u)), \
1137 "r" ((USItype)(v)) \
1138 : "%g1", "%g2" __AND_CLOBBER_CC)
1139 #define UMUL_TIME 39 /* 39 instructions */
1142 #ifndef LONGLONG_STANDALONE
1143 #define udiv_qrnnd(q, r, n1, n0, d) \
1145 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
1148 extern USItype __udiv_qrnnd ();
1149 #define UDIV_TIME 140
1150 #endif /* LONGLONG_STANDALONE */
1151 #endif /* udiv_qrnnd */
1152 #endif /* __sparc__ */
1154 #if defined (__vax__) && W_TYPE_SIZE == 32
1155 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1156 __asm__ ("addl2 %5,%1
1158 : "=g" ((USItype)(sh)), \
1159 "=&g" ((USItype)(sl)) \
1160 : "%0" ((USItype)(ah)), \
1161 "g" ((USItype)(bh)), \
1162 "%1" ((USItype)(al)), \
1163 "g" ((USItype)(bl)))
1164 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1165 __asm__ ("subl2 %5,%1
1167 : "=g" ((USItype)(sh)), \
1168 "=&g" ((USItype)(sl)) \
1169 : "0" ((USItype)(ah)), \
1170 "g" ((USItype)(bh)), \
1171 "1" ((USItype)(al)), \
1172 "g" ((USItype)(bl)))
1173 #define umul_ppmm(xh, xl, m0, m1) \
1175 union {UDItype __ll; \
1176 struct {USItype __l, __h;} __i; \
1178 USItype __m0 = (m0), __m1 = (m1); \
1179 __asm__ ("emul %1,%2,$0,%0" \
1180 : "=g" (__xx.__ll) \
1183 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1184 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1185 + (((SItype) __m1 >> 31) & __m0)); \
1187 #define sdiv_qrnnd(q, r, n1, n0, d) \
1189 union {DItype __ll; \
1190 struct {SItype __l, __h;} __i; \
1192 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1193 __asm__ ("ediv %3,%2,%0,%1" \
1194 : "=g" (q), "=g" (r) \
1195 : "g" (__xx.ll), "g" (d)); \
1197 #endif /* __vax__ */
1199 #if defined (__z8000__) && W_TYPE_SIZE == 16
1200 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1201 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1202 : "=r" ((unsigned int)(sh)), \
1203 "=&r" ((unsigned int)(sl)) \
1204 : "%0" ((unsigned int)(ah)), \
1205 "r" ((unsigned int)(bh)), \
1206 "%1" ((unsigned int)(al)), \
1207 "rQR" ((unsigned int)(bl)))
1208 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1209 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1210 : "=r" ((unsigned int)(sh)), \
1211 "=&r" ((unsigned int)(sl)) \
1212 : "0" ((unsigned int)(ah)), \
1213 "r" ((unsigned int)(bh)), \
1214 "1" ((unsigned int)(al)), \
1215 "rQR" ((unsigned int)(bl)))
1216 #define umul_ppmm(xh, xl, m0, m1) \
1218 union {long int __ll; \
1219 struct {unsigned int __h, __l;} __i; \
1221 unsigned int __m0 = (m0), __m1 = (m1); \
1222 __asm__ ("mult %S0,%H3" \
1223 : "=r" (__xx.__i.__h), \
1224 "=r" (__xx.__i.__l) \
1227 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1228 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1229 + (((signed int) __m1 >> 15) & __m0)); \
1231 #endif /* __z8000__ */
1233 #endif /* __GNUC__ */
1236 #if !defined (umul_ppmm) && defined (__umulsidi3)
1237 #define umul_ppmm(ph, pl, m0, m1) \
1239 UDWtype __ll = __umulsidi3 (m0, m1); \
1240 ph = (UWtype) (__ll >> W_TYPE_SIZE); \
1241 pl = (UWtype) __ll; \
1245 #if !defined (__umulsidi3)
1246 #define __umulsidi3(u, v) \
1247 ({UWtype __hi, __lo; \
1248 umul_ppmm (__hi, __lo, u, v); \
1249 ((UDWtype) __hi << W_TYPE_SIZE) | __lo; })
1252 /* If this machine has no inline assembler, use C macros. */
1254 #if !defined (add_ssaaaa)
1255 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1258 __x = (al) + (bl); \
1259 (sh) = (ah) + (bh) + (__x < (al)); \
1264 #if !defined (sub_ddmmss)
1265 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1268 __x = (al) - (bl); \
1269 (sh) = (ah) - (bh) - (__x > (al)); \
1274 #if !defined (umul_ppmm)
1275 #define umul_ppmm(w1, w0, u, v) \
1277 UWtype __x0, __x1, __x2, __x3; \
1278 UHWtype __ul, __vl, __uh, __vh; \
1279 UWtype __u = (u), __v = (v); \
1281 __ul = __ll_lowpart (__u); \
1282 __uh = __ll_highpart (__u); \
1283 __vl = __ll_lowpart (__v); \
1284 __vh = __ll_highpart (__v); \
1286 __x0 = (UWtype) __ul * __vl; \
1287 __x1 = (UWtype) __ul * __vh; \
1288 __x2 = (UWtype) __uh * __vl; \
1289 __x3 = (UWtype) __uh * __vh; \
1291 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1292 __x1 += __x2; /* but this indeed can */ \
1293 if (__x1 < __x2) /* did we get it? */ \
1294 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1296 (w1) = __x3 + __ll_highpart (__x1); \
1297 (w0) = (__ll_lowpart (__x1) << W_TYPE_SIZE/2) + __ll_lowpart (__x0);\
1301 #if !defined (umul_ppmm)
1302 #define smul_ppmm(w1, w0, u, v) \
1305 UWtype __m0 = (u), __m1 = (v); \
1306 umul_ppmm (__w1, w0, __m0, __m1); \
1307 (w1) = __w1 - (-(__m0 >> (W_TYPE_SIZE - 1)) & __m1) \
1308 - (-(__m1 >> (W_TYPE_SIZE - 1)) & __m0); \
1312 /* Define this unconditionally, so it can be used for debugging. */
1313 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1315 UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
1316 __d1 = __ll_highpart (d); \
1317 __d0 = __ll_lowpart (d); \
1319 __r1 = (n1) % __d1; \
1320 __q1 = (n1) / __d1; \
1321 __m = (UWtype) __q1 * __d0; \
1322 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1325 __q1--, __r1 += (d); \
1326 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1328 __q1--, __r1 += (d); \
1332 __r0 = __r1 % __d1; \
1333 __q0 = __r1 / __d1; \
1334 __m = (UWtype) __q0 * __d0; \
1335 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1338 __q0--, __r0 += (d); \
1341 __q0--, __r0 += (d); \
1345 (q) = (UWtype) __q1 * __ll_B | __q0; \
1349 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1350 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1351 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1352 #define udiv_qrnnd(q, r, nh, nl, d) \
1355 (q) = __MPN(udiv_w_sdiv) (&__r, nh, nl, d); \
1360 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1361 #if !defined (udiv_qrnnd)
1362 #define UDIV_NEEDS_NORMALIZATION 1
1363 #define udiv_qrnnd __udiv_qrnnd_c
1366 #if !defined (count_leading_zeros)
1371 unsigned char __clz_tab[];
1372 #define count_leading_zeros(count, x) \
1374 UWtype __xr = (x); \
1377 if (W_TYPE_SIZE <= 32) \
1379 __a = __xr < ((UWtype) 1 << 2*__BITS4) \
1380 ? (__xr < ((UWtype) 1 << __BITS4) ? 0 : __BITS4) \
1381 : (__xr < ((UWtype) 1 << 3*__BITS4) ? 2*__BITS4 : 3*__BITS4);\
1385 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1386 if (((__xr >> __a) & 0xff) != 0) \
1390 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1392 /* This version gives a well-defined value for zero. */
1393 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1396 #if !defined (count_trailing_zeros)
1397 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1398 defined in asm, but if it is not, the C version above is good enough. */
1399 #define count_trailing_zeros(count, x) \
1401 UWtype __ctz_x = (x); \
1403 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1404 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1408 #ifndef UDIV_NEEDS_NORMALIZATION
1409 #define UDIV_NEEDS_NORMALIZATION 0