Update Intel architecture guide references to latest.

[pintos-anon] / src / userprog / pagedir.c

diff --git a/src/userprog/pagedir.c b/src/userprog/pagedir.c
index 4604ca2ddf94b24e97f31fbd5d553b06ab3ff7c1..ea3c1f458409ec7c3b0771cbb3af1761d785c1ff 100644 (file)
--- a/src/userprog/pagedir.c
+++ b/src/userprog/pagedir.c
@@ -88,6 +88,8 @@ lookup_page (uint32_t *pd, const void *vaddr, bool create)
 /* Adds a mapping from user virtual page UPAGE to kernel virtual
    address KPAGE in page directory PD.
    UPAGE must not already be mapped.
+   KPAGE should probably be a page obtained from the user pool
+   with palloc_get_page().
    If WRITABLE is true, the new page is read/write;
    otherwise it is read-only.
    Returns true if successful, false if memory allocation
@@ -222,8 +224,9 @@ pagedir_activate (uint32_t *pd)
   /* Store the physical address of the page directory into CR3
      aka PDBR (page directory base register).  This activates our
      new page tables immediately.  See [IA32-v2a] "MOV--Move
-     to/from Control Registers" and [IA32-v3] 3.7.5. */
-  asm volatile ("mov %%cr3, %0" :: "r" (vtop (pd)));
+     to/from Control Registers" and [IA32-v3a] 3.7.5 "Base
+     Address of the Page Directory". */
+  asm volatile ("movl %0, %%cr3" :: "r" (vtop (pd)));
 }
 
 /* Returns the currently active page directory. */
@@ -233,9 +236,9 @@ active_pd (void)
   /* Copy CR3, the page directory base register (PDBR), into
      `pd'.
      See [IA32-v2a] "MOV--Move to/from Control Registers" and
-     [IA32-v3] 3.7.5. */
+     [IA32-v3a] 3.7.5 "Base Address of the Page Directory". */
   uintptr_t pd;
-  asm volatile ("mov %0, %%cr3" : "=r" (pd));
+  asm volatile ("movl %%cr3, %0" : "=r" (pd));
   return ptov (pd);
 }
 
@@ -252,9 +255,9 @@ invalidate_pagedir (uint32_t *pd)
 {
   if (active_pd () == pd) 
     {
-      /* We cleared a page-table entry in the active page
-         table, so we have to invalidate the TLB.  See
-         [IA32-v3], section 3.11. */
+      /* We cleared a page-table entry in the active page table,
+         so we have to invalidate the TLB.  See [IA32-v3a] 3.12
+         "Translation Lookaside Buffers (TLBs)". */
       pagedir_activate (pd);
     } 
 }