Update Intel architecture guide references to latest.

[pintos-anon] / src / threads / loader.S

diff --git a/src/threads/loader.S b/src/threads/loader.S
index fc834ffa45642eaba3203ab7f3c844f3305d11b5..2d76763cffc3dcdc2aa339404bfb674360e22ae1 100644 (file)
--- a/src/threads/loader.S
+++ b/src/threads/loader.S
@@ -138,7 +138,9 @@ start:
 
 # Add PDEs to point to PTEs for the first 64 MB of RAM.
 # Also add identical PDEs starting at LOADER_PHYS_BASE.
-# See [IA32-v3] section 3.7.6 for a description of the bits in %eax.
+# See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries"
+# for a description of the bits in %eax.
+       
 
        movl $0x11007, %eax
        movl $0x11, %ecx
@@ -150,7 +152,8 @@ start:
        loop 1b
 
 # Set up one-to-map linear to physical map for the first 64 MB of RAM.
-# See [IA32-v3] section 3.7.6 for a description of the bits in %eax.
+# See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries"
+# for a description of the bits in %eax.
 
        movw $0x1100, %ax
        movw %ax, %es