-#include "interrupt.h"
+#include "threads/interrupt.h"
+#include <debug.h>
+#include <inttypes.h>
#include <stdint.h>
-#include "debug.h"
-#include "io.h"
-#include "lib.h"
-#include "mmu.h"
-#include "thread.h"
-#include "timer.h"
+#include <stdio.h>
+#include "threads/flags.h"
+#include "threads/intr-stubs.h"
+#include "threads/io.h"
+#include "threads/thread.h"
+#include "threads/vaddr.h"
+#include "devices/timer.h"
+
+/* Programmable Interrupt Controller (PIC) registers.
+ A PC has two PICs, called the master and slave PICs, with the
+ slave attached ("cascaded") to the master IRQ line 2. */
+#define PIC0_CTRL 0x20 /* Master PIC control register address. */
+#define PIC0_DATA 0x21 /* Master PIC data register address. */
+#define PIC1_CTRL 0xa0 /* Slave PIC control register address. */
+#define PIC1_DATA 0xa1 /* Slave PIC data register address. */
+
+/* Number of x86 interrupts. */
+#define INTR_CNT 256
+
+/* The Interrupt Descriptor Table (IDT). The format is fixed by
+ the CPU. See [IA32-v3a] sections 5.10 "Interrupt Descriptor
+ Table (IDT)", 5.11 "IDT Descriptors", 5.12.1.2 "Flag Usage By
+ Exception- or Interrupt-Handler Procedure". */
+static uint64_t idt[INTR_CNT];
+
+/* Interrupt handler functions for each interrupt. */
+static intr_handler_func *intr_handlers[INTR_CNT];
+
+/* Names for each interrupt, for debugging purposes. */
+static const char *intr_names[INTR_CNT];
+
+/* External interrupts are those generated by devices outside the
+ CPU, such as the timer. External interrupts run with
+ interrupts turned off, so they never nest, nor are they ever
+ pre-empted. Handlers for external interrupts also may not
+ sleep, although they may invoke intr_yield_on_return() to
+ request that a new process be scheduled just before the
+ interrupt returns. */
+static bool in_external_intr; /* Are we processing an external interrupt? */
+static bool yield_on_return; /* Should we yield on interrupt return? */
+
+/* Programmable Interrupt Controller helpers. */
+static void pic_init (void);
+static void pic_end_of_interrupt (int irq);
+
+/* Interrupt Descriptor Table helpers. */
+static uint64_t make_intr_gate (void (*) (void), int dpl);
+static uint64_t make_trap_gate (void (*) (void), int dpl);
+static inline uint64_t make_idtr_operand (uint16_t limit, void *base);
+
+/* Interrupt handlers. */
+void intr_handler (struct intr_frame *args);
\f
-enum if_level
+/* Returns the current interrupt status. */
+enum intr_level
intr_get_level (void)
{
uint32_t flags;
-
- asm ("pushfl; popl %0" : "=g" (flags));
- return flags & (1 << 9) ? IF_ON : IF_OFF;
+ /* Push the flags register on the processor stack, then pop the
+ value off the stack into `flags'. See [IA32-v2b] "PUSHF"
+ and "POP" and [IA32-v3a] 5.8.1 "Masking Maskable Hardware
+ Interrupts". */
+ asm volatile ("pushfl; popl %0" : "=g" (flags));
+
+ return flags & FLAG_IF ? INTR_ON : INTR_OFF;
}
-enum if_level
-intr_set_level (enum if_level level)
+/* Enables or disables interrupts as specified by LEVEL and
+ returns the previous interrupt status. */
+enum intr_level
+intr_set_level (enum intr_level level)
{
- enum if_level old_level = intr_get_level ();
- if (level == IF_ON)
- intr_enable ();
- else
- intr_disable ();
- return old_level;
+ return level == INTR_ON ? intr_enable () : intr_disable ();
}
-enum if_level
+/* Enables interrupts and returns the previous interrupt status. */
+enum intr_level
intr_enable (void)
{
- enum if_level old_level = intr_get_level ();
+ enum intr_level old_level = intr_get_level ();
+ ASSERT (!intr_context ());
+
+ /* Enable interrupts by setting the interrupt flag.
+
+ See [IA32-v2b] "STI" and [IA32-v3a] 5.8.1 "Masking Maskable
+ Hardware Interrupts". */
asm volatile ("sti");
+
return old_level;
}
-enum if_level
+/* Disables interrupts and returns the previous interrupt status. */
+enum intr_level
intr_disable (void)
{
- enum if_level old_level = intr_get_level ();
- asm volatile ("cli");
+ enum intr_level old_level = intr_get_level ();
+
+ /* Disable interrupts by clearing the interrupt flag.
+ See [IA32-v2b] "CLI" and [IA32-v3a] 5.8.1 "Masking Maskable
+ Hardware Interrupts". */
+ asm volatile ("cli" : : : "memory");
+
return old_level;
}
\f
-static void
-pic_init (void)
+/* Initializes the interrupt system. */
+void
+intr_init (void)
{
- /* Every PC has two 8259A Programmable Interrupt Controller
- (PIC) chips. One is a "master" accessible at ports 0x20 and
- 0x21. The other is a "slave" cascaded onto the master's IRQ
- 2 line and accessible at ports 0xa0 and 0xa1. Accesses to
- port 0x20 set the A0 line to 0 and accesses to 0x21 set the
- A1 line to 1. The situation is similar for the slave PIC.
- Refer to the 8259A datasheet for details.
-
- By default, interrupts 0...15 delivered by the PICs will go
- to interrupt vectors 0...15. Unfortunately, those vectors
- are also used for CPU traps and exceptions. We reprogram
- the PICs so that interrupts 0...15 are delivered to
- interrupt vectors 32...47 instead. */
-
- /* Mask all interrupts on both PICs. */
- outb (0x21, 0xff);
- outb (0xa1, 0xff);
-
- /* Initialize master. */
- outb (0x20, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
- outb (0x21, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
- outb (0x21, 0x04); /* ICW3: slave PIC on line IR2. */
- outb (0x21, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
+ uint64_t idtr_operand;
+ int i;
- /* Initialize slave. */
- outb (0xa0, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
- outb (0xa1, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
- outb (0xa1, 0x02); /* ICW3: slave ID is 2. */
- outb (0xa1, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
+ /* Initialize interrupt controller. */
+ pic_init ();
- /* Unmask all interrupts. */
- outb (0x21, 0x00);
- outb (0xa1, 0x00);
+ /* Initialize IDT. */
+ for (i = 0; i < INTR_CNT; i++)
+ idt[i] = make_intr_gate (intr_stubs[i], 0);
+
+ /* Load IDT register.
+ See [IA32-v2a] "LIDT" and [IA32-v3a] 5.10 "Interrupt
+ Descriptor Table (IDT)". */
+ idtr_operand = make_idtr_operand (sizeof idt - 1, idt);
+ asm volatile ("lidt %0" : : "m" (idtr_operand));
+
+ /* Initialize intr_names. */
+ for (i = 0; i < INTR_CNT; i++)
+ intr_names[i] = "unknown";
+ intr_names[0] = "#DE Divide Error";
+ intr_names[1] = "#DB Debug Exception";
+ intr_names[2] = "NMI Interrupt";
+ intr_names[3] = "#BP Breakpoint Exception";
+ intr_names[4] = "#OF Overflow Exception";
+ intr_names[5] = "#BR BOUND Range Exceeded Exception";
+ intr_names[6] = "#UD Invalid Opcode Exception";
+ intr_names[7] = "#NM Device Not Available Exception";
+ intr_names[8] = "#DF Double Fault Exception";
+ intr_names[9] = "Coprocessor Segment Overrun";
+ intr_names[10] = "#TS Invalid TSS Exception";
+ intr_names[11] = "#NP Segment Not Present";
+ intr_names[12] = "#SS Stack Fault Exception";
+ intr_names[13] = "#GP General Protection Exception";
+ intr_names[14] = "#PF Page-Fault Exception";
+ intr_names[16] = "#MF x87 FPU Floating-Point Error";
+ intr_names[17] = "#AC Alignment Check Exception";
+ intr_names[18] = "#MC Machine-Check Exception";
+ intr_names[19] = "#XF SIMD Floating-Point Exception";
}
-/* Sends an end-of-interrupt signal to the PIC for the given IRQ.
- If we don't acknowledge the IRQ, we'll never get it again, so
- this is important. */
+/* Registers interrupt VEC_NO to invoke HANDLER with descriptor
+ privilege level DPL. Names the interrupt NAME for debugging
+ purposes. The interrupt handler will be invoked with
+ interrupt status set to LEVEL. */
static void
-pic_eoi (void)
+register_handler (uint8_t vec_no, int dpl, enum intr_level level,
+ intr_handler_func *handler, const char *name)
{
- /* FIXME? The Linux code is much more complicated. */
- outb (0x20, 0x20);
+ ASSERT (intr_handlers[vec_no] == NULL);
+ if (level == INTR_ON)
+ idt[vec_no] = make_trap_gate (intr_stubs[vec_no], dpl);
+ else
+ idt[vec_no] = make_intr_gate (intr_stubs[vec_no], dpl);
+ intr_handlers[vec_no] = handler;
+ intr_names[vec_no] = name;
}
-\f
-uint64_t idt[256];
-
-extern void (*intr_stubs[256]) (void);
-
-intr_handler_func *intr_handlers[256];
-
-void intr_handler (struct intr_frame *args);
-
-bool intr_in_progress;
-bool yield_on_return;
+/* Registers external interrupt VEC_NO to invoke HANDLER, which
+ is named NAME for debugging purposes. The handler will
+ execute with interrupts disabled. */
void
-intr_handler (struct intr_frame *args)
+intr_register_ext (uint8_t vec_no, intr_handler_func *handler,
+ const char *name)
{
- bool external;
-
- yield_on_return = false;
-
- external = args->vec_no >= 0x20 && args->vec_no < 0x30;
- if (external)
- {
- ASSERT (intr_get_level () == IF_OFF);
- ASSERT (!intr_context ());
- intr_in_progress = true;
- }
-
- intr_handlers[args->vec_no] (args);
-
- if (external)
- {
- ASSERT (intr_get_level () == IF_OFF);
- ASSERT (intr_context ());
- intr_in_progress = false;
- pic_eoi ();
- }
+ ASSERT (vec_no >= 0x20 && vec_no <= 0x2f);
+ register_handler (vec_no, 0, INTR_OFF, handler, name);
+}
- if (yield_on_return)
- {
- printk (".");
- thread_yield ();
- }
+/* Registers internal interrupt VEC_NO to invoke HANDLER, which
+ is named NAME for debugging purposes. The interrupt handler
+ will be invoked with interrupt status LEVEL.
+
+ The handler will have descriptor privilege level DPL, meaning
+ that it can be invoked intentionally when the processor is in
+ the DPL or lower-numbered ring. In practice, DPL==3 allows
+ user mode to invoke the interrupts and DPL==0 prevents such
+ invocation. Faults and exceptions that occur in user mode
+ still cause interrupts with DPL==0 to be invoked. See
+ [IA32-v3a] sections 4.5 "Privilege Levels" and 4.8.1.1
+ "Accessing Nonconforming Code Segments" for further
+ discussion. */
+void
+intr_register_int (uint8_t vec_no, int dpl, enum intr_level level,
+ intr_handler_func *handler, const char *name)
+{
+ ASSERT (vec_no < 0x20 || vec_no > 0x2f);
+ register_handler (vec_no, dpl, level, handler, name);
}
+/* Returns true during processing of an external interrupt
+ and false at all other times. */
bool
intr_context (void)
{
- return intr_in_progress;
+ return in_external_intr;
}
+/* During processing of an external interrupt, directs the
+ interrupt handler to yield to a new process just before
+ returning from the interrupt. May not be called at any other
+ time. */
void
intr_yield_on_return (void)
{
+ ASSERT (intr_context ());
yield_on_return = true;
}
+\f
+/* 8259A Programmable Interrupt Controller. */
+
+/* Initializes the PICs. Refer to [8259A] for details.
+
+ By default, interrupts 0...15 delivered by the PICs will go to
+ interrupt vectors 0...15. Those vectors are also used for CPU
+ traps and exceptions, so we reprogram the PICs so that
+ interrupts 0...15 are delivered to interrupt vectors 32...47
+ (0x20...0x2f) instead. */
+static void
+pic_init (void)
+{
+ /* Mask all interrupts on both PICs. */
+ outb (PIC0_DATA, 0xff);
+ outb (PIC1_DATA, 0xff);
+
+ /* Initialize master. */
+ outb (PIC0_CTRL, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
+ outb (PIC0_DATA, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
+ outb (PIC0_DATA, 0x04); /* ICW3: slave PIC on line IR2. */
+ outb (PIC0_DATA, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
+
+ /* Initialize slave. */
+ outb (PIC1_CTRL, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
+ outb (PIC1_DATA, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
+ outb (PIC1_DATA, 0x02); /* ICW3: slave ID is 2. */
+ outb (PIC1_DATA, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
+
+ /* Unmask all interrupts. */
+ outb (PIC0_DATA, 0x00);
+ outb (PIC1_DATA, 0x00);
+}
-/* Handles interrupts we don't know about. */
-intr_handler_func intr_unexpected;
-
-/* Handlers for CPU exceptions. */
-intr_handler_func excp00_divide_error;
-intr_handler_func excp01_debug;
-intr_handler_func excp02_nmi;
-intr_handler_func excp03_breakpoint;
-intr_handler_func excp04_overflow;
-intr_handler_func excp05_bound;
-intr_handler_func excp06_invalid_opcode;
-intr_handler_func excp07_device_not_available;
-intr_handler_func excp08_double_fault;
-intr_handler_func excp09_coprocessor_overrun;
-intr_handler_func excp0a_invalid_tss;
-intr_handler_func excp0b_segment_not_present;
-intr_handler_func excp0c_stack_fault;
-intr_handler_func excp0d_general_protection;
-intr_handler_func excp0e_page_fault;
-intr_handler_func excp10_fp_error;
-intr_handler_func excp11_alignment;
-intr_handler_func excp12_machine_check;
-intr_handler_func excp13_simd_error;
+/* Sends an end-of-interrupt signal to the PIC for the given IRQ.
+ If we don't acknowledge the IRQ, it will never be delivered to
+ us again, so this is important. */
+static void
+pic_end_of_interrupt (int irq)
+{
+ ASSERT (irq >= 0x20 && irq < 0x30);
+
+ /* Acknowledge master PIC. */
+ outb (0x20, 0x20);
+ /* Acknowledge slave PIC if this is a slave interrupt. */
+ if (irq >= 0x28)
+ outb (0xa0, 0x20);
+}
+\f
+/* Creates an gate that invokes FUNCTION.
+
+ The gate has descriptor privilege level DPL, meaning that it
+ can be invoked intentionally when the processor is in the DPL
+ or lower-numbered ring. In practice, DPL==3 allows user mode
+ to call into the gate and DPL==0 prevents such calls. Faults
+ and exceptions that occur in user mode still cause gates with
+ DPL==0 to be invoked. See [IA32-v3a] sections 4.5 "Privilege
+ Levels" and 4.8.1.1 "Accessing Nonconforming Code Segments"
+ for further discussion.
+
+ TYPE must be either 14 (for an interrupt gate) or 15 (for a
+ trap gate). The difference is that entering an interrupt gate
+ disables interrupts, but entering a trap gate does not. See
+ [IA32-v3a] section 5.12.1.2 "Flag Usage By Exception- or
+ Interrupt-Handler Procedure" for discussion. */
static uint64_t
-make_intr_gate (void (*target) (void),
- int dpl)
+make_gate (void (*function) (void), int dpl, int type)
{
- uint32_t offset = (uint32_t) target;
- uint32_t e0 = ((offset & 0xffff) /* Offset 15:0. */
- | (SEL_KCSEG << 16)); /* Target code segment. */
- uint32_t e1 = ((offset & 0xffff0000) /* Offset 31:16. */
- | (1 << 15) /* Present. */
- | (dpl << 13) /* Descriptor privilege. */
- | (SYS_SYSTEM << 12) /* System. */
- | (TYPE_INT_32 << 8)); /* 32-bit interrupt gate. */
+ uint32_t e0, e1;
+
+ ASSERT (function != NULL);
+ ASSERT (dpl >= 0 && dpl <= 3);
+ ASSERT (type >= 0 && type <= 15);
+
+ e0 = (((uint32_t) function & 0xffff) /* Offset 15:0. */
+ | (SEL_KCSEG << 16)); /* Target code segment. */
+
+ e1 = (((uint32_t) function & 0xffff0000) /* Offset 31:16. */
+ | (1 << 15) /* Present. */
+ | ((uint32_t) dpl << 13) /* Descriptor privilege level. */
+ | (0 << 12) /* System. */
+ | ((uint32_t) type << 8)); /* Gate type. */
+
return e0 | ((uint64_t) e1 << 32);
}
+/* Creates an interrupt gate that invokes FUNCTION with the given
+ DPL. */
static uint64_t
-make_trap_gate (void (*target) (void),
- int dpl)
+make_intr_gate (void (*function) (void), int dpl)
{
- return make_intr_gate (target, dpl) | (1 << 8);
+ return make_gate (function, dpl, 14);
}
-/* We don't support nested interrupts generated by external
- hardware, so these interrupts (vec_no 0x20...0x2f) should
- specify IF_OFF for LEVEL. Otherwise a timer interrupt could
- cause a task switch during interrupt handling. Most other
- interrupts can and should be handled with interrupts
- enabled. */
-void
-intr_register (uint8_t vec_no, int dpl, enum if_level level,
- intr_handler_func *handler)
+/* Creates a trap gate that invokes FUNCTION with the given
+ DPL. */
+static uint64_t
+make_trap_gate (void (*function) (void), int dpl)
{
- if (level == IF_ON)
- idt[vec_no] = make_trap_gate (intr_stubs[vec_no], dpl);
- else
- idt[vec_no] = make_intr_gate (intr_stubs[vec_no], dpl);
- intr_handlers[vec_no] = handler;
+ return make_gate (function, dpl, 15);
+}
+
+/* Returns a descriptor that yields the given LIMIT and BASE when
+ used as an operand for the LIDT instruction. */
+static inline uint64_t
+make_idtr_operand (uint16_t limit, void *base)
+{
+ return limit | ((uint64_t) (uint32_t) base << 16);
}
+\f
+/* Interrupt handlers. */
+/* Handler for all interrupts, faults, and exceptions. This
+ function is called by the assembly language interrupt stubs in
+ intr-stubs.S. FRAME describes the interrupt and the
+ interrupted thread's registers. */
void
-intr_init (void)
+intr_handler (struct intr_frame *frame)
{
- uint64_t idtr_operand;
- int i;
+ bool external;
+ intr_handler_func *handler;
- pic_init ();
+ /* External interrupts are special.
+ We only handle one at a time (so interrupts must be off)
+ and they need to be acknowledged on the PIC (see below).
+ An external interrupt handler cannot sleep. */
+ external = frame->vec_no >= 0x20 && frame->vec_no < 0x30;
+ if (external)
+ {
+ ASSERT (intr_get_level () == INTR_OFF);
+ ASSERT (!intr_context ());
+
+ in_external_intr = true;
+ yield_on_return = false;
+ }
+
+ /* Invoke the interrupt's handler. */
+ handler = intr_handlers[frame->vec_no];
+ if (handler != NULL)
+ handler (frame);
+ else if (frame->vec_no == 0x27 || frame->vec_no == 0x2f)
+ {
+ /* There is no handler, but this interrupt can trigger
+ spuriously due to a hardware fault or hardware race
+ condition. Ignore it. */
+ }
+ else
+ {
+ /* No handler and not spurious. Invoke the unexpected
+ interrupt handler. */
+ intr_dump_frame (frame);
+ PANIC ("Unexpected interrupt");
+ }
+
+ /* Complete the processing of an external interrupt. */
+ if (external)
+ {
+ ASSERT (intr_get_level () == INTR_OFF);
+ ASSERT (intr_context ());
- /* Install default handlers. */
- for (i = 0; i < 256; i++)
- intr_register (i, 0, IF_OFF, intr_unexpected);
-
- /* Most exceptions require ring 0.
- Exceptions 3, 4, and 5 can be caused by ring 3 directly.
-
- Most exceptions can be handled with interrupts turned on.
- We need to disable interrupts for page faults because the
- fault address is stored in CR2 and needs to be preserved.
- */
-#if 0
- intr_register (0x00, 0, IF_ON, excp00_divide_error);
- intr_register (0x01, 0, IF_ON, excp01_debug);
- intr_register (0x02, 0, IF_ON, excp02_nmi);
- intr_register (0x03, 3, IF_ON, excp03_breakpoint);
- intr_register (0x04, 3, IF_ON, excp04_overflow);
- intr_register (0x05, 3, IF_ON, excp05_bound);
- intr_register (0x06, 0, IF_ON, excp06_invalid_opcode);
- intr_register (0x07, 0, IF_ON, excp07_device_not_available);
- intr_register (0x08, 0, IF_ON, excp08_double_fault);
- intr_register (0x09, 0, IF_ON, excp09_coprocessor_overrun);
- intr_register (0x0a, 0, IF_ON, excp0a_invalid_tss);
- intr_register (0x0b, 0, IF_ON, excp0b_segment_not_present);
- intr_register (0x0c, 0, IF_ON, excp0c_stack_fault);
- intr_register (0x0d, 0, IF_ON, excp0d_general_protection);
- intr_register (0x0e, 0, IF_OFF, excp0e_page_fault);
- intr_register (0x10, 0, IF_ON, excp10_fp_error);
- intr_register (0x11, 0, IF_ON, excp11_alignment);
- intr_register (0x12, 0, IF_ON, excp12_machine_check);
- intr_register (0x13, 0, IF_ON, excp13_simd_error);
-#endif
-
- idtr_operand = make_dtr_operand (sizeof idt - 1, idt);
- asm volatile ("lidt %0" :: "m" (idtr_operand));
+ in_external_intr = false;
+ pic_end_of_interrupt (frame->vec_no);
+
+ if (yield_on_return)
+ thread_yield ();
+ }
}
+/* Dumps interrupt frame F to the console, for debugging. */
void
-intr_unexpected (struct intr_frame *regs)
+intr_dump_frame (const struct intr_frame *f)
{
uint32_t cr2;
+
+ /* Store current value of CR2 into `cr2'.
+ CR2 is the linear address of the last page fault.
+ See [IA32-v2a] "MOV--Move to/from Control Registers" and
+ [IA32-v3a] 5.14 "Interrupt 14--Page Fault Exception
+ (#PF)". */
asm ("movl %%cr2, %0" : "=r" (cr2));
- panic ("Unexpected interrupt 0x%02x, error code %08x, cr2=%08x, eip=%p",
- regs->vec_no, regs->error_code, cr2, (void *) regs->eip);
+
+ printf ("Interrupt %#04x (%s) at eip=%p\n",
+ f->vec_no, intr_names[f->vec_no], f->eip);
+ printf (" cr2=%08"PRIx32" error=%08"PRIx32"\n", cr2, f->error_code);
+ printf (" eax=%08"PRIx32" ebx=%08"PRIx32" ecx=%08"PRIx32" edx=%08"PRIx32"\n",
+ f->eax, f->ebx, f->ecx, f->edx);
+ printf (" esi=%08"PRIx32" edi=%08"PRIx32" esp=%08"PRIx32" ebp=%08"PRIx32"\n",
+ f->esi, f->edi, (uint32_t) f->esp, f->ebp);
+ printf (" cs=%04"PRIx16" ds=%04"PRIx16" es=%04"PRIx16" ss=%04"PRIx16"\n",
+ f->cs, f->ds, f->es, f->ss);
+}
+
+/* Returns the name of interrupt VEC. */
+const char *
+intr_name (uint8_t vec)
+{
+ return intr_names[vec];
}
projects / pintos-anon / blobdiff