#include "threads/flags.h"
#include "threads/intr-stubs.h"
#include "threads/io.h"
-#include "threads/mmu.h"
#include "threads/thread.h"
+#include "threads/vaddr.h"
#include "devices/timer.h"
+/* Programmable Interrupt Controller (PIC) registers.
+ A PC has two PICs, called the master and slave PICs, with the
+ slave attached ("cascaded") to the master IRQ line 2. */
+#define PIC0_CTRL 0x20 /* Master PIC control register address. */
+#define PIC0_DATA 0x21 /* Master PIC data register address. */
+#define PIC1_CTRL 0xa0 /* Slave PIC control register address. */
+#define PIC1_DATA 0xa1 /* Slave PIC data register address. */
+
/* Number of x86 interrupts. */
#define INTR_CNT 256
/* The Interrupt Descriptor Table (IDT). The format is fixed by
- the CPU. See [IA32-v3] sections 5.10, 5.11, 5.12.1.2. */
+ the CPU. See [IA32-v3a] sections 5.10 "Interrupt Descriptor
+ Table (IDT)", 5.11 "IDT Descriptors", 5.12.1.2 "Flag Usage By
+ Exception- or Interrupt-Handler Procedure". */
static uint64_t idt[INTR_CNT];
/* Interrupt handler functions for each interrupt. */
/* Push the flags register on the processor stack, then pop the
value off the stack into `flags'. See [IA32-v2b] "PUSHF"
- and "POP" and [IA32-v3] 5.8.1. */
+ and "POP" and [IA32-v3a] 5.8.1 "Masking Maskable Hardware
+ Interrupts". */
asm volatile ("pushfl; popl %0" : "=g" (flags));
return flags & FLAG_IF ? INTR_ON : INTR_OFF;
ASSERT (!intr_context ());
/* Enable interrupts by setting the interrupt flag.
- See [IA32-v2b] "STI" and [IA32-v3] 5.8.1. */
+
+ See [IA32-v2b] "STI" and [IA32-v3a] 5.8.1 "Masking Maskable
+ Hardware Interrupts". */
asm volatile ("sti");
return old_level;
enum intr_level old_level = intr_get_level ();
/* Disable interrupts by clearing the interrupt flag.
- See [IA32-v2b] "CLI" and [IA32-v3] 5.8.1. */
- asm volatile ("cli");
+ See [IA32-v2b] "CLI" and [IA32-v3a] 5.8.1 "Masking Maskable
+ Hardware Interrupts". */
+ asm volatile ("cli" : : : "memory");
return old_level;
}
idt[i] = make_intr_gate (intr_stubs[i], 0);
/* Load IDT register.
- See [IA32-v2a] "LIDT" and [IA32-v3] 5.10. */
+ See [IA32-v2a] "LIDT" and [IA32-v3a] 5.10 "Interrupt
+ Descriptor Table (IDT)". */
idtr_operand = make_idtr_operand (sizeof idt - 1, idt);
- asm volatile ("lidt %0" :: "m" (idtr_operand));
+ asm volatile ("lidt %0" : : "m" (idtr_operand));
/* Initialize intr_names. */
for (i = 0; i < INTR_CNT; i++)
user mode to invoke the interrupts and DPL==0 prevents such
invocation. Faults and exceptions that occur in user mode
still cause interrupts with DPL==0 to be invoked. See
- [IA32-v3] sections 4.5 and 4.8.1.1 for further discussion. */
+ [IA32-v3a] sections 4.5 "Privilege Levels" and 4.8.1.1
+ "Accessing Nonconforming Code Segments" for further
+ discussion. */
void
intr_register_int (uint8_t vec_no, int dpl, enum intr_level level,
intr_handler_func *handler, const char *name)
\f
/* 8259A Programmable Interrupt Controller. */
-/* Every PC has two 8259A Programmable Interrupt Controller (PIC)
- chips. One is a "master" accessible at ports 0x20 and 0x21.
- The other is a "slave" cascaded onto the master's IRQ 2 line
- and accessible at ports 0xa0 and 0xa1. Accesses to port 0x20
- set the A0 line to 0 and accesses to 0x21 set the A1 line to
- 1. The situation is similar for the slave PIC.
+/* Initializes the PICs. Refer to [8259A] for details.
By default, interrupts 0...15 delivered by the PICs will go to
- interrupt vectors 0...15. Unfortunately, those vectors are
- also used for CPU traps and exceptions. We reprogram the PICs
- so that interrupts 0...15 are delivered to interrupt vectors
- 32...47 (0x20...0x2f) instead. */
-
-/* Initializes the PICs. Refer to [8259A] for details. */
+ interrupt vectors 0...15. Those vectors are also used for CPU
+ traps and exceptions, so we reprogram the PICs so that
+ interrupts 0...15 are delivered to interrupt vectors 32...47
+ (0x20...0x2f) instead. */
static void
pic_init (void)
{
/* Mask all interrupts on both PICs. */
- outb (0x21, 0xff);
- outb (0xa1, 0xff);
+ outb (PIC0_DATA, 0xff);
+ outb (PIC1_DATA, 0xff);
/* Initialize master. */
- outb (0x20, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
- outb (0x21, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
- outb (0x21, 0x04); /* ICW3: slave PIC on line IR2. */
- outb (0x21, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
+ outb (PIC0_CTRL, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
+ outb (PIC0_DATA, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
+ outb (PIC0_DATA, 0x04); /* ICW3: slave PIC on line IR2. */
+ outb (PIC0_DATA, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
/* Initialize slave. */
- outb (0xa0, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
- outb (0xa1, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
- outb (0xa1, 0x02); /* ICW3: slave ID is 2. */
- outb (0xa1, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
+ outb (PIC1_CTRL, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
+ outb (PIC1_DATA, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
+ outb (PIC1_DATA, 0x02); /* ICW3: slave ID is 2. */
+ outb (PIC1_DATA, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
/* Unmask all interrupts. */
- outb (0x21, 0x00);
- outb (0xa1, 0x00);
+ outb (PIC0_DATA, 0x00);
+ outb (PIC1_DATA, 0x00);
}
/* Sends an end-of-interrupt signal to the PIC for the given IRQ.
or lower-numbered ring. In practice, DPL==3 allows user mode
to call into the gate and DPL==0 prevents such calls. Faults
and exceptions that occur in user mode still cause gates with
- DPL==0 to be invoked. See [IA32-v3] sections 4.5 and 4.8.1.1
+ DPL==0 to be invoked. See [IA32-v3a] sections 4.5 "Privilege
+ Levels" and 4.8.1.1 "Accessing Nonconforming Code Segments"
for further discussion.
TYPE must be either 14 (for an interrupt gate) or 15 (for a
trap gate). The difference is that entering an interrupt gate
disables interrupts, but entering a trap gate does not. See
- [IA32-v3] section 5.12.1.2 for discussion. */
+ [IA32-v3a] section 5.12.1.2 "Flag Usage By Exception- or
+ Interrupt-Handler Procedure" for discussion. */
static uint64_t
make_gate (void (*function) (void), int dpl, int type)
{
yield_on_return = false;
}
- /* Invoke the interrupt's handler.
- If there is no handler, invoke the unexpected interrupt
- handler. */
+ /* Invoke the interrupt's handler. */
handler = intr_handlers[frame->vec_no];
- if (handler == NULL)
+ if (handler != NULL)
+ handler (frame);
+ else if (frame->vec_no == 0x27 || frame->vec_no == 0x2f)
+ {
+ /* There is no handler, but this interrupt can trigger
+ spuriously due to a hardware fault or hardware race
+ condition. Ignore it. */
+ }
+ else
{
+ /* No handler and not spurious. Invoke the unexpected
+ interrupt handler. */
intr_dump_frame (frame);
- PANIC ("Unexpected interrupt");
+ PANIC ("Unexpected interrupt");
}
- handler (frame);
/* Complete the processing of an external interrupt. */
if (external)
/* Store current value of CR2 into `cr2'.
CR2 is the linear address of the last page fault.
See [IA32-v2a] "MOV--Move to/from Control Registers" and
- [IA32-v3] 5.14 "Interrupt 14--Page Fault Exception
+ [IA32-v3a] 5.14 "Interrupt 14--Page Fault Exception
(#PF)". */
asm ("movl %%cr2, %0" : "=r" (cr2));
projects / pintos-anon / blobdiff