return &pt[pt_no (vaddr)];
}
-/* Adds a mapping from user virtual page UPAGE to kernel virtual
- address KPAGE in page directory PD.
+/* Adds a mapping in page directory PD from user virtual page
+ UPAGE to the physical frame identified by kernel virtual
+ address KPAGE.
UPAGE must not already be mapped.
KPAGE should probably be a page obtained from the user pool
- with palloc_get_page() .
+ with palloc_get_page().
If WRITABLE is true, the new page is read/write;
otherwise it is read-only.
Returns true if successful, false if memory allocation
failed. */
bool
-pagedir_set_page (uint32_t *pd, void *upage, void *kpage,
- bool writable)
+pagedir_set_page (uint32_t *pd, void *upage, void *kpage, bool writable)
{
uint32_t *pte;
return false;
}
-/* Returns the kernel virtual address that user virtual address
- UADDR is mapped to in PD, or a null pointer if UADDR is not
- present. */
+/* Looks up the physical address that corresponds to user virtual
+ address UADDR in PD. Returns the kernel virtual address
+ corresponding to that physical address, or a null pointer if
+ UADDR is unmapped. */
void *
pagedir_get_page (uint32_t *pd, const void *uaddr)
{
/* Store the physical address of the page directory into CR3
aka PDBR (page directory base register). This activates our
new page tables immediately. See [IA32-v2a] "MOV--Move
- to/from Control Registers" and [IA32-v3] 3.7.5. */
+ to/from Control Registers" and [IA32-v3a] 3.7.5 "Base
+ Address of the Page Directory". */
asm volatile ("movl %0, %%cr3" :: "r" (vtop (pd)));
}
/* Copy CR3, the page directory base register (PDBR), into
`pd'.
See [IA32-v2a] "MOV--Move to/from Control Registers" and
- [IA32-v3] 3.7.5. */
+ [IA32-v3a] 3.7.5 "Base Address of the Page Directory". */
uintptr_t pd;
asm volatile ("movl %%cr3, %0" : "=r" (pd));
return ptov (pd);
{
if (active_pd () == pd)
{
- /* We cleared a page-table entry in the active page
- table, so we have to invalidate the TLB. See
- [IA32-v3], section 3.11. */
+ /* Re-activating PD clears the TLB. See [IA32-v3a] 3.12
+ "Translation Lookaside Buffers (TLBs)". */
pagedir_activate (pd);
}
}