- /* Copy CR3, the page directory base register (PDBR), into `pd'
- for us to exmaine. See [IA32-v2a] "MOV--Move to/from
- Control Registers" and [IA32-v3] 3.7.5. */
- asm ("movl %%cr3,%0" : "=r" (pd));
- return pd;
+/* Seom page table changes can cause the CPU's translation
+ lookaside buffer (TLB) to become out-of-sync with the page
+ table. When this happens, we have to "invalidate" the TLB by
+ re-activating it.
+
+ This function invalidates the TLB if PD is the active page
+ directory. (If PD is not active then its entries are not in
+ the TLB, so there is no need to invalidate anything.) */
+static void
+invalidate_pagedir (uint32_t *pd)
+{
+ if (active_pd () == pd)
+ {
+ /* We cleared a page-table entry in the active page table,
+ so we have to invalidate the TLB. See [IA32-v3a] 3.12
+ "Translation Lookaside Buffers (TLBs)". */
+ pagedir_activate (pd);
+ }