+
+/** masks a given IRQ */
+void intr_irq_mask(int irq)
+{
+ if(irq < 8){
+ pic_mask[0] |= 1 << irq;
+ outb (PIC0_DATA, pic_mask[0]);
+ }else{
+ pic_mask[1] |= 1 << (irq - 8);
+ outb (PIC1_DATA, pic_mask[1]);
+ }
+}
+
+/** unmasks a given IRQ */
+void intr_irq_unmask(int irq)
+{
+ if(irq >= 8){
+ /* enable cascade if not enabled for pic2 */
+ if(pic_mask[1] & (1 << (IRQ_CASCADE1 - 8)))
+ pic_mask[1] &= ~(1 << (IRQ_CASCADE1 - 8));
+
+ pic_mask[1] &= ~(1 << (irq - 8));
+ outb(PIC1_DATA, pic_mask[1]);
+
+ /* enable cascade if not enabled for pic1 */
+ if(pic_mask[0] & (1 << IRQ_CASCADE0))
+ irq = IRQ_CASCADE0;
+ }
+
+ if(irq < 8){
+ pic_mask[0] &= ~(1 << irq);
+ outb (PIC0_DATA, pic_mask[0]);
+ }
+
+}
+
+/* return whether an interrupt vector is registered */
+bool intr_is_registered(uint8_t vec_no)
+{
+ return (intr_handlers[vec_no] != NULL);
+}