+#define PCI_BAD_DEVICE 0xffff
+
+/* PCI-to-PCI bridge related numbers */
+#define PCI_BRIDGE_BASE_CLASS 0x06
+#define PCI_BRIDGE_SUB_CLASS 0x04
+#define PCI_BRIDGE_REG_SBUS 0x19
+#define PCI_BRIDGE_HEADER_TYPE 0x01
+
+/* Locations of registers in the configuration space */
+#define PCI_REG_CLASS_INTERFACE 0x09
+#define PCI_REG_CLASS_SUB 0x0a
+#define PCI_REG_CLASS_BASE 0x0b
+#define PCI_REG_HEADER_TYPE 0x0e
+#define PCI_REGNUM_BASE_ADDRESS 4
+
+/* Base address related numbers */
+#define PCI_NUM_BARS 6
+#define PCI_BAR_TYPE_MASK 0x1
+#define PCI_BAR_TYPE_MEM 0x0
+#define PCI_BAR_TYPE_IO 0x1
+#define PCI_BAR_MASK_MEM 0xfffffff0
+#define PCI_BAR_MASK_IO 0xfffffffc
+
+struct pci_dev
+{