1 /* This file is derived from source code used in MIT's 6.828
2 course. The original copyright notice is reproduced in full
6 * Copyright (C) 1997 Massachusetts Institute of Technology
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41 #include "threads/loader.h"
45 #### This code should be stored in the first sector of the hard disk.
46 #### When the BIOS runs, it loads this code at physical address
47 #### 0x7c00-0x7e00 (512 bytes). Then it jumps to the beginning of it,
48 #### in real mode. This code switches into protected mode (32-bit
49 #### mode) so that all of memory can accessed, loads the kernel into
50 #### memory, and jumps to the first byte of the kernel, where start.S
53 /* Flags in control register 0. */
54 #define CR0_PE 0x00000001 /* Protection Enable. */
55 #define CR0_EM 0x00000004 /* (Floating-point) Emulation. */
56 #define CR0_PG 0x80000000 /* Paging. */
57 #define CR0_WP 0x00010000 /* Write-Protect enable in kernel mode. */
63 # Code runs in real mode, which is a 16-bit segment.
66 # Disable interrupts, because we will not be prepared to handle them
67 # in protected mode until much later.
68 # String instructions go upward (e.g. for "rep stosl" below).
73 # Set up data segments.
79 # Set up stack segment.
80 # Stack grows downward starting from us.
81 # We don't ever use the stack, but we call into the BIOS,
87 #### Enable A20. Address line 20 is tied to low when the machine
88 #### boots, which prevents addressing memory about 1 MB. This code
91 # Poll status register while busy.
97 # Send command for writing output port.
102 # Poll status register while busy.
113 #### Get memory size, via interrupt 15h function 88h. Returns CF
114 #### clear if successful, with AX = (kB of physical memory) - 1024.
115 #### This only works for memory sizes <= 65 MB, which should be fine
116 #### for our purposes. We cap memory at 64 MB because that's all we
117 #### prepare page tables for, below.
122 cli # BIOS might have enabled interrupts
123 addl $1024, %eax # Total kB memory
124 cmp $0x10000, %eax # Cap at 64 MB
127 1: shrl $2, %eax # Total 4 kB pages
130 #### Create temporary page directory and page table and set page
131 #### directory base register.
133 # Create page directory at 64 kB and fill with zeroes.
141 # Add PDEs to point to PTEs for the first 64 MB of RAM.
142 # Also add identical PDEs starting at LOADER_PHYS_BASE.
143 # See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries"
144 # for a description of the bits in %eax.
150 1: movl %eax, %es:(%di)
151 movl %eax, %es:LOADER_PHYS_BASE >> 20(%di)
156 # Set up one-to-map linear to physical map for the first 64 MB of RAM.
157 # See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries"
158 # for a description of the bits in %eax.
165 1: movl %eax, %es:(%di)
170 # Set page directory base register.
175 #### Switch to protected mode.
177 # Note that interrupts are still off.
179 # Point the GDTR to our GDT. Protected mode requires a GDT.
180 # We need a data32 prefix to ensure that all 32 bits of the GDT
181 # descriptor are loaded (default is to load only 24 bits).
185 # Then we turn on the following bits in CR0:
186 # PE (Protect Enable): this turns on protected mode.
187 # PG (Paging): turns on paging.
188 # WP (Write Protect): if unset, ring 0 code ignores
189 # write-protect bits in page tables (!).
190 # EM (Emulation): forces floating-point instructions to trap.
191 # We don't support floating point.
194 orl $CR0_PE | CR0_PG | CR0_WP | CR0_EM, %eax
197 # We're now in protected mode in a 16-bit segment. The CPU still has
198 # the real-mode code segment cached in %cs's segment descriptor. We
199 # need to reload %cs, and the easiest way is to use a far jump.
200 # Because we're not in a 32-bit segment the data32 prefix is needed to
201 # jump to a 32-bit offset.
203 data32 ljmp $SEL_KCSEG, $1f + LOADER_PHYS_BASE
205 # We're now in protected mode in a 32-bit segment.
209 # Reload all the other segment registers and the stack pointer to
210 # point into our new GDT.
212 1: movw $SEL_KDSEG, %ax
218 movl $LOADER_PHYS_BASE + 0x30000, %esp
220 #### Load kernel starting at physical address LOADER_KERN_BASE by
221 #### frobbing the IDE controller directly.
224 movl $LOADER_KERN_BASE + LOADER_PHYS_BASE, %edi
226 # Disable interrupt delivery by IDE controller, because we will be
228 # (If we don't do this, Bochs 2.2.6 will never deliver any IDE
229 # interrupt to us later after we reset the interrupt controller during
230 # boot, even if we also reset the IDE controller.)
238 # Poll status register while controller busy.
245 # Read a single sector.
251 # Sector number to write in low 28 bits.
252 # LBA mode, device 0 in top 4 bits.
255 andl $0x0fffffff, %eax
256 orl $0xe0000000, %eax
258 # Dump %eax to ports 0x1f3...0x1f6.
266 # READ command to command register.
272 # Poll status register while controller busy.
278 # Poll status register until data ready.
293 cmpl $KERNEL_LOAD_PAGES*8 + 1, %ebx
296 #### Jump to kernel entry point.
298 movl $LOADER_PHYS_BASE + LOADER_KERN_BASE, %eax
305 .quad 0x0000000000000000 # null seg
306 .quad 0x00cf9a000000ffff # code seg
307 .quad 0x00cf92000000ffff # data seg
310 .word 0x17 # sizeof (gdt) - 1
311 .long gdt + LOADER_PHYS_BASE # address gdt
314 #### Print panic_message (with help from the BIOS) and spin.
316 panic: .code16 # We only panic in real mode.
317 movw $panic_message, %si
330 #### Physical memory size in 4 kB pages.
331 #### This is initialized by the loader and read by the kernel.
332 .org LOADER_RAM_PGS - LOADER_BASE
336 #### Command-line arguments and their count.
337 #### This is written by the `pintos' utility and read by the kernel.
338 #### The loader itself does not do anything with the command line.
339 .org LOADER_ARG_CNT - LOADER_BASE
342 .org LOADER_ARGS - LOADER_BASE
346 #### Boot-sector signature.
347 #### The BIOS checks that this is set properly.
348 .org LOADER_SIG - LOADER_BASE