1 #include "threads/interrupt.h"
6 #include "threads/flags.h"
7 #include "threads/intr-stubs.h"
8 #include "threads/io.h"
9 #include "threads/mmu.h"
10 #include "threads/thread.h"
11 #include "devices/timer.h"
13 /* Number of x86 interrupts. */
16 /* The Interrupt Descriptor Table (IDT). The format is fixed by
17 the CPU. See [IA32-v3] sections 5.10, 5.11, 5.12.1.2. */
18 static uint64_t idt[INTR_CNT];
20 /* Interrupt handler functions for each interrupt. */
21 static intr_handler_func *intr_handlers[INTR_CNT];
23 /* Names for each interrupt, for debugging purposes. */
24 static const char *intr_names[INTR_CNT];
26 /* External interrupts are those generated by devices outside the
27 CPU, such as the timer. External interrupts run with
28 interrupts turned off, so they never nest, nor are they ever
29 pre-empted. Handlers for external interrupts also may not
30 sleep, although they may invoke intr_yield_on_return() to
31 request that a new process be scheduled just before the
33 static bool in_external_intr; /* Are we processing an external interrupt? */
34 static bool yield_on_return; /* Should we yield on interrupt return? */
36 /* Programmable Interrupt Controller helpers. */
37 static void pic_init (void);
38 static void pic_end_of_interrupt (int irq);
40 /* Interrupt Descriptor Table helpers. */
41 static uint64_t make_intr_gate (void (*) (void), int dpl);
42 static uint64_t make_trap_gate (void (*) (void), int dpl);
43 static inline uint64_t make_idtr_operand (uint16_t limit, void *base);
45 /* Interrupt handlers. */
46 void intr_handler (struct intr_frame *args);
48 /* Returns the current interrupt status. */
54 /* Push the flags register on the processor stack, then pop the
55 value off the stack into `flags'. See [IA32-v2b] "PUSHF"
56 and "POP" and [IA32-v3] 5.8.1. */
57 asm volatile ("pushf; pop %0" : "=g" (flags));
59 return flags & FLAG_IF ? INTR_ON : INTR_OFF;
62 /* Enables or disables interrupts as specified by LEVEL and
63 returns the previous interrupt status. */
65 intr_set_level (enum intr_level level)
67 return level == INTR_ON ? intr_enable () : intr_disable ();
70 /* Enables interrupts and returns the previous interrupt status. */
74 enum intr_level old_level = intr_get_level ();
75 ASSERT (!intr_context ());
77 /* Enable interrupts by setting the interrupt flag.
78 See [IA32-v2b] "STI" and [IA32-v3] 5.8.1. */
84 /* Disables interrupts and returns the previous interrupt status. */
88 enum intr_level old_level = intr_get_level ();
90 /* Disable interrupts by clearing the interrupt flag.
91 See [IA32-v2b] "CLI" and [IA32-v3] 5.8.1. */
97 /* Initializes the interrupt system. */
101 uint64_t idtr_operand;
104 /* Initialize interrupt controller. */
107 /* Initialize IDT. */
108 for (i = 0; i < INTR_CNT; i++)
109 idt[i] = make_intr_gate (intr_stubs[i], 0);
111 /* Load IDT register.
112 See [IA32-v2a] "LIDT" and [IA32-v3] 5.10. */
113 idtr_operand = make_idtr_operand (sizeof idt - 1, idt);
114 asm volatile ("lidt %0" :: "m" (idtr_operand));
116 /* Initialize intr_names. */
117 for (i = 0; i < INTR_CNT; i++)
118 intr_names[i] = "unknown";
119 intr_names[0] = "#DE Divide Error";
120 intr_names[1] = "#DB Debug Exception";
121 intr_names[2] = "NMI Interrupt";
122 intr_names[3] = "#BP Breakpoint Exception";
123 intr_names[4] = "#OF Overflow Exception";
124 intr_names[5] = "#BR BOUND Range Exceeded Exception";
125 intr_names[6] = "#UD Invalid Opcode Exception";
126 intr_names[7] = "#NM Device Not Available Exception";
127 intr_names[8] = "#DF Double Fault Exception";
128 intr_names[9] = "Coprocessor Segment Overrun";
129 intr_names[10] = "#TS Invalid TSS Exception";
130 intr_names[11] = "#NP Segment Not Present";
131 intr_names[12] = "#SS Stack Fault Exception";
132 intr_names[13] = "#GP General Protection Exception";
133 intr_names[14] = "#PF Page-Fault Exception";
134 intr_names[16] = "#MF x87 FPU Floating-Point Error";
135 intr_names[17] = "#AC Alignment Check Exception";
136 intr_names[18] = "#MC Machine-Check Exception";
137 intr_names[19] = "#XF SIMD Floating-Point Exception";
140 /* Registers interrupt VEC_NO to invoke HANDLER, which is named
141 NAME for debugging purposes. The interrupt handler will be
142 invoked with interrupt status set to LEVEL.
144 The handler will have descriptor privilege level DPL, meaning
145 that it can be invoked intentionally when the processor is in
146 the DPL or lower-numbered ring. In practice, DPL==3 allows
147 user mode to invoke the interrupts and DPL==0 prevents such
148 invocation. Faults and exceptions that occur in user mode
149 still cause interrupts with DPL==0 to be invoked. See
150 [IA32-v3] sections 4.5 and 4.8.1.1 for further discussion. */
152 intr_register (uint8_t vec_no, int dpl, enum intr_level level,
153 intr_handler_func *handler,
156 /* Make sure this handler isn't already registered to someone
158 ASSERT (intr_handlers[vec_no] == NULL);
160 /* Interrupts generated by external hardware (0x20 <= VEC_NO <=
161 0x2f) should specify INTR_OFF for LEVEL. Otherwise a timer
162 interrupt could cause a task switch during interrupt
163 handling. Most other interrupts can and should be handled
164 with interrupts enabled. */
165 ASSERT (vec_no < 0x20 || vec_no > 0x2f || level == INTR_OFF);
167 if (level == INTR_ON)
168 idt[vec_no] = make_trap_gate (intr_stubs[vec_no], dpl);
170 idt[vec_no] = make_intr_gate (intr_stubs[vec_no], dpl);
171 intr_handlers[vec_no] = handler;
172 intr_names[vec_no] = name;
175 /* Returns true during processing of an external interrupt
176 and false at all other times. */
180 return in_external_intr;
183 /* During processing of an external interrupt, directs the
184 interrupt handler to yield to a new process just before
185 returning from the interrupt. May not be called at any other
188 intr_yield_on_return (void)
190 ASSERT (intr_context ());
191 yield_on_return = true;
194 /* 8259A Programmable Interrupt Controller. */
196 /* Every PC has two 8259A Programmable Interrupt Controller (PIC)
197 chips. One is a "master" accessible at ports 0x20 and 0x21.
198 The other is a "slave" cascaded onto the master's IRQ 2 line
199 and accessible at ports 0xa0 and 0xa1. Accesses to port 0x20
200 set the A0 line to 0 and accesses to 0x21 set the A1 line to
201 1. The situation is similar for the slave PIC.
203 By default, interrupts 0...15 delivered by the PICs will go to
204 interrupt vectors 0...15. Unfortunately, those vectors are
205 also used for CPU traps and exceptions. We reprogram the PICs
206 so that interrupts 0...15 are delivered to interrupt vectors
207 32...47 (0x20...0x2f) instead. */
209 /* Initializes the PICs. Refer to [8259A] for details. */
213 /* Mask all interrupts on both PICs. */
217 /* Initialize master. */
218 outb (0x20, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
219 outb (0x21, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
220 outb (0x21, 0x04); /* ICW3: slave PIC on line IR2. */
221 outb (0x21, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
223 /* Initialize slave. */
224 outb (0xa0, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
225 outb (0xa1, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
226 outb (0xa1, 0x02); /* ICW3: slave ID is 2. */
227 outb (0xa1, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
229 /* Unmask all interrupts. */
234 /* Sends an end-of-interrupt signal to the PIC for the given IRQ.
235 If we don't acknowledge the IRQ, it will never be delivered to
236 us again, so this is important. */
238 pic_end_of_interrupt (int irq)
240 ASSERT (irq >= 0x20 && irq < 0x30);
242 /* Acknowledge master PIC. */
245 /* Acknowledge slave PIC if this is a slave interrupt. */
250 /* Creates an gate that invokes FUNCTION.
252 The gate has descriptor privilege level DPL, meaning that it
253 can be invoked intentionally when the processor is in the DPL
254 or lower-numbered ring. In practice, DPL==3 allows user mode
255 to call into the gate and DPL==0 prevents such calls. Faults
256 and exceptions that occur in user mode still cause gates with
257 DPL==0 to be invoked. See [IA32-v3] sections 4.5 and 4.8.1.1
258 for further discussion.
260 TYPE must be either 14 (for an interrupt gate) or 15 (for a
261 trap gate). The difference is that entering an interrupt gate
262 disables interrupts, but entering a trap gate does not. See
263 [IA32-v3] section 5.12.1.2 for discussion. */
265 make_gate (void (*function) (void), int dpl, int type)
269 ASSERT (function != NULL);
270 ASSERT (dpl >= 0 && dpl <= 3);
271 ASSERT (type >= 0 && type <= 15);
273 e0 = (((uint32_t) function & 0xffff) /* Offset 15:0. */
274 | (SEL_KCSEG << 16)); /* Target code segment. */
276 e1 = (((uint32_t) function & 0xffff0000) /* Offset 31:16. */
277 | (1 << 15) /* Present. */
278 | ((uint32_t) dpl << 13) /* Descriptor privilege level. */
279 | (0 << 12) /* System. */
280 | ((uint32_t) type << 8)); /* Gate type. */
282 return e0 | ((uint64_t) e1 << 32);
285 /* Creates an interrupt gate that invokes FUNCTION with the given
288 make_intr_gate (void (*function) (void), int dpl)
290 return make_gate (function, dpl, 14);
293 /* Creates a trap gate that invokes FUNCTION with the given
296 make_trap_gate (void (*function) (void), int dpl)
298 return make_gate (function, dpl, 15);
301 /* Returns a descriptor that yields the given LIMIT and BASE when
302 used as an operand for the LIDT instruction. */
303 static inline uint64_t
304 make_idtr_operand (uint16_t limit, void *base)
306 return limit | ((uint64_t) (uint32_t) base << 16);
309 /* Interrupt handlers. */
311 /* Handler for all interrupts, faults, and exceptions. This
312 function is called by the assembly language interrupt stubs in
313 intr-stubs.S. FRAME describes the interrupt and the
314 interrupted thread's registers. */
316 intr_handler (struct intr_frame *frame)
319 intr_handler_func *handler;
321 /* External interrupts are special.
322 We only handle one at a time (so interrupts must be off)
323 and they need to be acknowledged on the PIC (see below).
324 An external interrupt handler cannot sleep. */
325 external = frame->vec_no >= 0x20 && frame->vec_no < 0x30;
328 ASSERT (intr_get_level () == INTR_OFF);
329 ASSERT (!intr_context ());
331 in_external_intr = true;
332 yield_on_return = false;
335 /* Invoke the interrupt's handler.
336 If there is no handler, invoke the unexpected interrupt
338 handler = intr_handlers[frame->vec_no];
341 intr_dump_frame (frame);
342 PANIC ("Unexpected interrupt");
346 /* Complete the processing of an external interrupt. */
349 ASSERT (intr_get_level () == INTR_OFF);
350 ASSERT (intr_context ());
352 in_external_intr = false;
353 pic_end_of_interrupt (frame->vec_no);
360 /* Dumps interrupt frame F to the console, for debugging. */
362 intr_dump_frame (const struct intr_frame *f)
366 /* Store current value of CR2 into `cr2'.
367 CR2 is the linear address of the last page fault.
368 See [IA32-v2a] "MOV--Move to/from Control Registers" and
369 [IA32-v3] 5.14 "Interrupt 14--Page Fault Exception
371 asm ("mov %0, %%cr2" : "=r" (cr2));
373 printf ("Interrupt %#04x (%s) at eip=%p\n",
374 f->vec_no, intr_names[f->vec_no], f->eip);
375 printf (" cr2=%08"PRIx32" error=%08"PRIx32"\n", cr2, f->error_code);
376 printf (" eax=%08"PRIx32" ebx=%08"PRIx32" ecx=%08"PRIx32" edx=%08"PRIx32"\n",
377 f->eax, f->ebx, f->ecx, f->edx);
378 printf (" esi=%08"PRIx32" edi=%08"PRIx32" esp=%08"PRIx32" ebp=%08"PRIx32"\n",
379 f->esi, f->edi, (uint32_t) f->esp, f->ebp);
380 printf (" cs=%04"PRIx16" ds=%04"PRIx16" es=%04"PRIx16" ss=%04"PRIx16"\n",
381 f->cs, f->ds, f->es, f->ss);
384 /* Returns the name of interrupt VEC. */
386 intr_name (uint8_t vec)
388 return intr_names[vec];