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4 <META NAME="Author" CONTENT="Joshua Neal">
5 <META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and otherlow-level stuff.)">
6 <META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
7 <TITLE>VGA/SVGA Video Programming--Accessing the VGA Display Memory</TITLE>
11 <CENTER><A HREF="../home.htm">Home</A> <A HREF="#intro">Intro</A> <A HREF="#detect">Detecting</A>
12 <A HREF="#mapping">Mapping</A> <A HREF="#address">Addressing</A> <A HREF="#manip">Manipulating</A>
13 <A HREF="#read">Reading</A> <A HREF="#write">Writing</A> <A HREF="vga.htm#general">Back</A>
14 <HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
17 <CENTER>Accessing the VGA Display Memory
18 <HR WIDTH="100%"></CENTER>
22 <A HREF="#intro">Introduction</A> -- gives an overview of the VGA display
26 <A HREF="#detect">Detecting the Amount of Display Memory on the Adapter</A>
27 -- details how to determine the amount of memory present on the VGA.</LI>
30 <A HREF="#mapping">Mapping of Display Memory into CPU Address Space</A>
31 -- details how to control the location and size of the memory aperture.</LI>
34 <A HREF="#address">Host Address to Display Address Translation</A> -- detail
35 how the VGA hardware maps a host access to a display memory access</LI>
38 <A HREF="#manip">Manipulating Display Memory</A> -- Details on reading
39 and writing to VGA memory</LI>
43 <A HREF="#read">Reading from Display Memory</A> -- Details the hardware
44 mechanisms used when reading display memory.</LI>
47 <A HREF="#write">Writing to Display Memory</A> -- Details the hardware
48 mechanisms used when writing display memory.</LI>
51 <A NAME="intro"></A><B>Introduction</B>
52 <BR> The standard VGA hardware
53 contains up to 256K of onboard display memory. While it would seem logical
54 that this memory would be directly available to the processor, this is
55 not the case. The host CPU accesses the display memory through a window
56 of up to 128K located in the high memory area. (Note that many SVGA chipsets
57 provide an alternate method of accessing video memory directly, called
58 a Linear Frame Buffer.) Thus in order to be able to access display memory
59 you must deal with registers that control the mapping into host address
60 space. To further complicate things, the VGA hardware provides support
61 for memory models similar to that used by the monochrome, CGA, EGA, and
62 MCGA adapters. In addition, due to the way the VGA handles 16 color modes,
63 additional hardware is included that can speed access immensely. Also,
64 hardware is present that allows the programer to rapidly copy data from
65 one area of display memory to another. While it is quite complicated to
66 understand, learning to utilize the VGA's hardware at a low level can vastly
67 improve performance. Many game programmers utilize the BIOS mode 13h, simply
68 because it offers the simplest memory model and doesn't require having
69 to deal with the VGA's registers to draw pixels. However, this same decision
70 limits them from being able to use the infamous X modes, or higher resolution
73 <P><A NAME="detect"></A><B>Detecting the Amount of Display Memory on the
75 <BR><B> </B>Most VGA cards in
76 existence have 256K on board; however there is the possibility that some
77 VGA boards have less. To actually determine further if the card has 256K
78 one must actually write to display memory and read back values. If RAM
79 is not present in a location, then the value read back will not equal the
80 value written. It is wise to utilize multiple values when doing this, as
81 the undefined result may equal the value written. Also, the card may alias
82 addresses, causing say the same 64K of RAM to appear 4 times in the 256K
83 address space, thus it is wise to change an address and see if the change
84 is reflected anywhere else in display memory. In addition, the card may
85 buffer one location of video memory in the chipset, making it appear that
86 there is RAM at an address where there is none present, so you may have
87 to read or write to a second location to clear the buffer. Not that if
88 the <A HREF="seqreg.htm#04">Extended Memory</A> field is not set to 1,
89 the adapter appears to only have 64K onboard, thus this bit should be set
90 to 1 before attempting to determine the memory size.
92 <P><A NAME="mapping"></A><B>Mapping of Display Memory into CPU Address
94 <BR> The first element that defines
95 this mapping is whether or not the VGA decodes accesses from the CPU. This
96 is controlled by the <A HREF="extreg.htm#3CCR3C2W">RAM Enable</A> field.
97 If display memory decoding is disabled, then the VGA hardware ignores writes
98 to its address space. The address range that the VGA hardware decodes is
99 based upon the <A HREF="graphreg.htm#06">Memory Map Select</A> field. The
100 following table shows the address ranges in absolute 32-bit form decoded
101 for each value of this field:
104 00 -- A0000h-BFFFFh -- 128K</LI>
107 01 -- A0000h-AFFFFh -- 64K</LI>
110 10 -- B0000h-B7FFFh -- 32K</LI>
113 11 -- B8000h-BFFFFh -- 32K</LI>
115 Note -- It would seem that by setting the <A HREF="graphreg.htm#06">Memory
116 Map Select</A> field to 00 and then using planar memory access that you
117 could gain access to more than 256K of memory on an SVGA card. However,
118 I have found that some cards simply mirror the first 64K twice within the
119 128K address space. This memory map is intended for use in the Chain Odd/Even
120 modes, eliminating the need to use the Odd/Even Page Select field. Also
121 I have found that MS-DOS memory managers don't like this very much and
122 are likely to lock up the system if configured to use the area from B0000h-B7FFFh
123 for loading device drivers high.
125 <P><A NAME="address"></A><B>Host Address to Display Address Translation</B>
126 <BR> The most complicated part
127 of accessing display memory involves the translation between a host address
128 and a display memory address. Internally, the VGA has a 64K 32-bit memory
129 locations. These are divided into four 64K bit planes. Because the VGA
130 was designed for 8 and 16 bit bus systems, and due to the way the Intel
131 chips handle memory accesses, it is impossible for the host CPU to access
132 the bit planes directly, instead relying on I/O registers to make part
133 of the memory accessible. The most straightforward display translation
134 is where a host access translates directly to a display memory address.
135 What part of the particular 32-bit memory location is dependent on certain
136 registers and is discussed in more detail in Manipulating Display Memory
137 below. The VGA has three modes for addressing, Chain 4, Odd/Even mode,
141 Chain 4: This mode is used for MCGA emulation in the 320x200 256-color
142 mode. The address is mapped to memory MOD 4 (shifted right 2 places.)</LI>
144 <B><More to be added here.></B>
146 <P><A NAME="manip"></A><B>Manipulating Display Memory</B>
147 <BR> The VGA hardware contains
148 hardware that can perform bit manipulation on data and allow the host to
149 operate on all four display planes in a single operation. These features
150 are fairly straightforward, yet complicated enough that most VGA programmers
151 choose to ignore them. This is unfortunate, as properly utilization of
152 these registers is crucial to programming the VGA's 16 color modes. Also,
153 knowledge of this functionality can in many cases enhance performance in
154 other modes including text and 256 color modes. In addition to normal read
155 and write operations the VGA hardware provides enhanced operations such
156 as the ability to perform rapid comparisons, to write to multiple planes
157 simultaneously, and to rapidly move data from one area of display memory
158 to another, faster logical operations (AND/OR/XOR) as well as bit rotation
161 <P><A NAME="read"></A><B>Reading from Display Memory</B>
162 <BR> The VGA hardware has two
163 read modes, selected by the <A HREF="graphreg.htm#05">Read Mode</A> field.
164 The first is a straightforward read of one or more consecutive bytes (depending
165 on whether a byte, word or dword operation is used) from one bit plane.
166 The value of the <A HREF="graphreg.htm#04">Read Map Select</A> field is
167 the page that will be read from. The second read mode returns the result
168 of a comparison of the display memory and the <A HREF="graphreg.htm#02">Color
169 Compare</A> field and masked by the <A HREF="graphreg.htm#07">Color Don't
170 Care</A> field. This mode which can be used to rapidly perform up to 32
171 pixel comparisons in one operation in the planar video modes, helpful for
172 the implementation of fast flood-fill routines. A read from display memory
173 also loads a 32 bit latch register, one byte from each plane. This latch
174 register, is not directly accessible from the host CPU; rather it can be
175 used as data for the various write operations. The latch register retains
176 its value until the next read and thus may be used with more than one write
178 <BR> The two read modes, simply called
179 Read Mode 0-1 based on the value of the <A HREF="graphreg.htm#05">Read
183 <B>Read Mode 0:</B></LI>
185 <BR> Read Mode 0 is used to read one
186 byte from a single plane of display memory. The plane read is the value
187 of the <A HREF="graphreg.htm#04">Read Map Select</A> field. In order to
188 read a single pixel's value in planar modes, four read operations must
189 be performed, one for each plane. If more than one bytes worth of data
190 is being read from the screen it is recommended that you read it a plane
191 at a time instead of having to perform four I/O operations to the <A HREF="graphreg.htm#04">Read
192 Map Select</A> field for each byte, as this will allow the use of faster
193 string copy instructions and reduce the number I/O operations performed.
195 <B>Read Mode 1:</B></LI>
197 <BR> Read Mode 1 is used to perform
198 comparisons against a reference color, specified by the <A HREF="graphreg.htm#02">Color
199 Compare</A> field. If a bit is set in the <A HREF="graphreg.htm#07">Color
200 Don't Care</A> field then the corresponding color plane is considered for
201 by the comparison, otherwise it is ignored. Each bit in the returned result
202 represents one comparison between the reference color from the <A HREF="graphreg.htm#02">Color
203 Compare</A> field, with the bit being set if the comparison is true. This
204 mode is mainly used by flood fill algorithms that fill an area of a specific
205 color, as it requires 1/4 the number of reads to determine the area that
206 needs to be filled in addition to the additional work done by the comparison.
207 Also an efficient "search and replace" operation that replaces one color
208 with another can be performed when this mode is combined with Write Mode
210 <A NAME="write"></A><B>Writing to Display Memory</B>
211 <BR> The VGA has four write modes,
212 selected by the <A HREF="graphreg.htm#05">Write Mode</A> field. This controls
213 how the write operation and host data affect the display memory. The VGA,
214 depending on the <A HREF="graphreg.htm#05">Write Mode</A> field performs
215 up to five distinct operations before the write affects display memory.
216 Note that not all write modes use all of pipelined stages in the write
217 hardware, and others use some of the pipelined stages in different ways.
218 <BR> The first of these allows
219 the VGA hardware to perform a bitwise rotation on the data written from
220 the host. This is accomplished via a barrel rotator that rotates the bits
221 to the right by the number of positions specified by the <A HREF="graphreg.htm#03">Rotate
222 Count</A> field. This performs the same operation as the 8086 ROR instruction,
223 shifting bits to the right (from bit 7 towards bit 0.) with the bit shifted
224 out of position 0 being "rolled" into position 7. Note that if the rotate
225 count field is zero then no rotation is performed.
226 <BR> The second uses the <A HREF="graphreg.htm#01">Enable
227 Set/Reset</A> and <A HREF="graphreg.htm#00">Set/Reset</A> fields. These
228 fields can provide an additional data source in addition to the data written
229 and the latched value from the last read operation performed. Normally,
230 data from the host is replicated four times, one for each plane. In this
231 stage, a 1 bit in the <A HREF="graphreg.htm#01">Enable Set/Reset</A> field
232 will cause the corresponding bit plane to be replaced by the bit value
233 in the corresponding <A HREF="graphreg.htm#00">Set/Reset</A> field location,
234 replicated 8 times to fill the byte, giving it either the value 00000000b
235 or 11111111b. If the <A HREF="graphreg.htm#01">Enable Set/Reset</A> field
236 for a given plane is 0 then the host data byte is used instead. Note that
237 in some write modes, the host data byte is used for other purposes, and
238 the set/reset register is always used as data, and in other modes the set/reset
239 mechanism is not used at all.
240 <BR> The third stage performs logical operations
241 between the host data, which has been split into four planes and is now
242 32-bits wide, and the latch register, which provides a second 32-bit operand.
243 The <A HREF="graphreg.htm#03">Logical Operation</A> field selects the operation
244 that this stage performs. The four possibilities are: NOP (the host data
245 is passed directly through, performing no operation), AND (the data is
246 logically ANDed with the latched data.), OR (the data is logically ORed
247 with the latched data), and XOR (the data is logically XORed with the latched
248 data.) The result of this operation is then passed on. whilst the latched
249 data remains unchanged, available for use in successive operations.
250 <BR> In the fourth stage, individual
251 bits may be selected from the result or copied from the latch register.
252 Each bit of the <A HREF="graphreg.htm#08">Bit Mask</A> field determines
253 whether the corresponding bits in each plane are the result of the previous
254 step or are copied directly from the latch register. This allows the host
255 CPU to modify only a single bit, by first performing a dummy read to fill
257 <BR> The fifth stage allows specification
258 of what planes, if any a write operation affects, via the <A HREF="seqreg.htm#02">Memory
259 Plane Write Enable</A> field. The four bits in this field determine whether
260 or not the write affects the corresponding plane If the a planes bit is
261 1 then the data from the previous step will be written to display memory,
262 otherwise the display buffer location in that plane will remain unchanged.
263 <BR> The four write modes, of
264 which the current one is set by writing to the <A HREF="graphreg.htm#05">Write
265 Mode</A> field The four write modes, simply called write modes 0-3, based
266 on the value of the <A HREF="graphreg.htm#05">Write Mode</A> field are:
269 <B>Write Mode 0:</B></LI>
271 <BR> Write Mode 0 is the standard
272 and most general write mode. While the other write modes are designed to
273 perform a specific task, this mode can be used to perform most tasks as
274 all five operations are performed on the data. The data byte from the host
275 is first rotated as specified by the <A HREF="graphreg.htm#03">Rotate Count</A>
276 field, then is replicated across all four planes. Then the <A HREF="graphreg.htm#01">Enable
277 Set/Reset</A> field selects which planes will receive their values from
278 the host data and which will receive their data from that plane's <A HREF="graphreg.htm#00">Set/Reset</A>
279 field location. Then the operation specified by the <A HREF="graphreg.htm#03">Logical
280 Operation</A> field is performed on the resulting data and the data in
281 the read latches. The <A HREF="graphreg.htm#08">Bit Mask</A> field is then
282 used to select between the resulting data and data from the latch register.
283 Finally, the resulting data is written to the display memory planes enabled
284 in the <A HREF="seqreg.htm#02">Memory Plane Write Enable</A> field.
286 <B>Write Mode 1:</B></LI>
288 <BR> Write Mode 1 is used to
289 transfer the data in the latches register directly to the screen, affected
290 only by the <A HREF="seqreg.htm#02">Memory Plane Write Enable</A> field.
291 This can facilitate rapid transfer of data on byte boundaries from one
292 area of video memory to another or filling areas of the display with a
293 pattern of 8 pixels. When Write Mode 0 is used with the <A HREF="graphreg.htm#08">Bit
294 Mask</A> field set to 00000000b the operation of the hardware is identical
295 to this mode, although it is entirely possible that this mode is faster
298 <B>Write Mode 2:</B></LI>
300 <BR> Write Mode 2 is used to
301 unpack a pixel value packed into the lower 4 bits of the host data byte
302 into the 4 display planes. In the byte from the host, the bit representing
303 each plane will be replicated across all 8 bits of the corresponding planes.
304 Then the operation specified by the <A HREF="graphreg.htm#03">Logical Operation</A>
305 field is performed on the resulting data and the data in the read latches.
306 The <A HREF="graphreg.htm#08">Bit Mask</A> field is then used to select
307 between the resulting data and data from the latch register. Finally, the
308 resulting data is written to the display memory planes enabled in the <A HREF="seqreg.htm#02">Memory
309 Plane Write Enable</A> field.
311 <B>Write Mode 3:</B></LI>
313 <BR><B> </B>Write Mode 3 is used
314 when the color written is fairly constant but the <A HREF="graphreg.htm#08">Bit
315 Mask</A> field needs to be changed frequently, such as when drawing single
316 color lines or text. The value of the <A HREF="graphreg.htm#00">Set/Reset</A>
317 field is expanded as if the <A HREF="graphreg.htm#01">Enable Set/Reset</A>
318 field were set to 1111b, regardless of its actual value. The host data
319 is first rotated as specified by the <A HREF="graphreg.htm#03">Rotate Count</A>
320 field, then is ANDed with the <A HREF="graphreg.htm#08">Bit Mask</A> field.
321 The resulting value is used where the <A HREF="graphreg.htm#08">Bit Mask</A>
322 field normally would be used, selecting data from either the expansion
323 of the <A HREF="graphreg.htm#00">Set/Reset</A> field or the latch register.
324 Finally, the resulting data is written to the display memory planes enabled
325 in the <A HREF="seqreg.htm#02">Memory Plane Write Enable</A> field.</UL>
326 Notice: All trademarks used or referred to on this page are the property
327 of their respective owners.
328 <BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
329 noted. Permission for utilization and distribution is subject to the terms
330 of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.
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