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5 <META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and other low-level stuff.)">
6 <META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
7 <TITLE>VGA/SVGA Video Programming--Graphics Registers</TITLE>
11 <CENTER><A HREF="../home.htm">Home</A> <A HREF="vga.htm#register">Back</A>
12 <HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
15 <CENTER>Graphics Registers
16 <HR WIDTH="100%"></CENTER>
19 <P> The Graphics Registers are
20 accessed via a pair of registers, the Graphics Address Register and the
21 Graphics Data Register. See the <A HREF="vgareg.htm">Accessing the VGA
22 Registers</A> section for more details. The Address Register is located
23 at port 3CEh and the Data Register is located at port 3CFh.
26 Index 00h -- Set/Reset Register</LI>
29 Index 01h -- Enable Set/Reset Register</LI>
32 Index 02h -- Color Compare Register</LI>
35 Index 03h -- Data Rotate Register</LI>
38 Index 04h -- Read Map Select Register</LI>
41 Index 05h -- <I>Graphics Mode Register</I></LI>
44 Index 06h -- <I>Miscellaneous Graphics Register</I></LI>
47 Index 07h -- Color Don't Care Register</LI>
50 Index 08h -- Bit Mask Register</LI>
53 <TABLE BORDER WIDTH="600" CELLPADING="2" >
54 <CAPTION ALIGN=TOP><A NAME="00"></A><B>Set/Reset Register (Index 00h)</B></CAPTION>
56 <TR ALIGN=CENTER VALIGN=CENTER>
74 <TR ALIGN=CENTER VALIGN=CENTER>
83 <TD COLSPAN="4" WIDTH="300">Set/Reset</TD>
91 <BR>Bits 3-0 of this field represent planes 3-0 of the VGA display memory.
92 This field is used by Write Mode 0 and Write Mode 3 (See the <A HREF="#05">Write
93 Mode</A> field.) In Write Mode 0, if the corresponding bit in the <A HREF="#01">Enable
94 Set/Reset</A> field is set, and in Write Mode 3 regardless of the <A HREF="#01">Enable
95 Set/Reset</A> field, the value of the bit in this field is expanded to
96 8 bits and substituted for the data of the respective plane and passed
97 to the next stage in the graphics pipeline, which for Write Mode 0 is the
98 <A HREF="#03">Logical Operation</A> unit and for Write Mode 3 is the <A HREF="#08">Bit
101 <TABLE BORDER WIDTH="600" CELLPADING="2" >
102 <CAPTION ALIGN=TOP><A NAME="01"></A><B>Enable Set/Reset Register (Index
105 <TR ALIGN=CENTER VALIGN=CENTER>
106 <TD WIDTH="75">7</TD>
108 <TD WIDTH="75">6</TD>
110 <TD WIDTH="75">5</TD>
112 <TD WIDTH="75">4</TD>
114 <TD WIDTH="75">3</TD>
116 <TD WIDTH="75">2</TD>
118 <TD WIDTH="75">1</TD>
120 <TD WIDTH="75">0</TD>
123 <TR ALIGN=CENTER VALIGN=CENTER>
132 <TD COLSPAN="4" WIDTH="300">Enable Set/Reset</TD>
138 <B>Enable Set/Reset</B></LI>
140 <BR>Bits 3-0 of this field represent planes 3-0 of the VGA display memory.
141 This field is used in Write Mode 0 (See the <A HREF="#05">Write Mode</A>
142 field) to select whether data for each plane is derived from host data
143 or from expansion of the respective bit in the <A HREF="#00">Set/Reset</A>
146 <TABLE BORDER WIDTH="600" CELLPADING="2" >
147 <CAPTION ALIGN=TOP><A NAME="02"></A><B>Color Compare Register (Index 02h)</B></CAPTION>
149 <TR ALIGN=CENTER VALIGN=CENTER>
150 <TD WIDTH="75">7</TD>
152 <TD WIDTH="75">6</TD>
154 <TD WIDTH="75">5</TD>
156 <TD WIDTH="75">4</TD>
158 <TD WIDTH="75">3</TD>
160 <TD WIDTH="75">2</TD>
162 <TD WIDTH="75">1</TD>
164 <TD WIDTH="75">0</TD>
167 <TR ALIGN=CENTER VALIGN=CENTER>
176 <TD COLSPAN="4" WIDTH="300">Color Compare</TD>
182 <B>Color Compare</B></LI>
184 <BR>Bits 3-0 of this field represent planes 3-0 of the VGA display memory.
185 This field holds a reference color that is used by Read Mode 1 (See the
186 <A HREF="#05">Read Mode</A> field.) Read Mode 1 returns the result of the
187 comparison between this value and a location of display memory, modified
188 by the <A HREF="#07">Color Don't Care</A> field.</UL>
190 <TABLE BORDER WIDTH="600" CELLPADING="2" >
191 <CAPTION ALIGN=TOP><A NAME="03"></A><B>Data Rotate Register (Index 03h)</B></CAPTION>
193 <TR ALIGN=CENTER VALIGN=CENTER>
194 <TD WIDTH="75">7</TD>
196 <TD WIDTH="75">6</TD>
198 <TD WIDTH="75">5</TD>
200 <TD WIDTH="75">4</TD>
202 <TD WIDTH="75">3</TD>
204 <TD WIDTH="75">2</TD>
206 <TD WIDTH="75">1</TD>
208 <TD WIDTH="75">0</TD>
211 <TR ALIGN=CENTER VALIGN=CENTER>
218 <TD COLSPAN="2" WIDTH="150">Logical Operation</TD>
220 <TD COLSPAN="3" WIDTH="225">Rotate Count</TD>
226 <B>Logical Operation</B></LI>
228 <BR>This field is used in Write Mode 0 and Write Mode 2 (See the <A HREF="#05">Write
229 Mode</A> field.) The logical operation stage of the graphics pipeline is
230 32 bits wide (1 byte * 4 planes) and performs the operations on its inputs
231 from the previous stage in the graphics pipeline and the latch register.
232 The latch register remains unchanged and the result is passed on to the
233 next stage in the pipeline. The results based on the value of this field
237 00b - Result is input from previous stage unmodified.</LI>
240 01b - Result is input from previous stage logical ANDed with latch register.</LI>
243 10b - Result is input from previous stage logical ORed with latch register.</LI>
246 11b - Result is input from previous stage logical XORed with latch register.</LI>
250 <B>Rotate Count</B></LI>
252 <BR>This field is used in Write Mode 0 and Write Mode 3 (See the <A HREF="#05">Write
253 Mode</A> field.) In these modes, the host data is rotated to the right
254 by the value specified by the value of this field. A rotation operation
255 consists of moving bits 7-1 right one position to bits 6-0, simultaneously
256 wrapping bit 0 around to bit 7, and is repeated the number of times specified
259 <TABLE BORDER WIDTH="600" CELLPADING="2" >
260 <CAPTION ALIGN=TOP><A NAME="04"></A><B>Read Map Select Register (Index
263 <TR ALIGN=CENTER VALIGN=CENTER>
264 <TD WIDTH="75">7</TD>
266 <TD WIDTH="75">6</TD>
268 <TD WIDTH="75">5</TD>
270 <TD WIDTH="75">4</TD>
272 <TD WIDTH="75">3</TD>
274 <TD WIDTH="75">2</TD>
276 <TD WIDTH="75">1</TD>
278 <TD WIDTH="75">0</TD>
281 <TR ALIGN=CENTER VALIGN=CENTER>
294 <TD COLSPAN="2" WIDTH="150">Read Map Select</TD>
300 <B>Read Map Select</B></LI>
302 <BR>This value of this field is used in Read Mode 0 (see the <A HREF="#05">Read
303 Mode</A> field) to specify the display memory plane to transfer data from.
304 Due to the arrangement of video memory, this field must be modified four
305 times to read one or more pixels values in the planar video modes.</UL>
307 <TABLE BORDER WIDTH="600" CELLPADING="2" >
308 <CAPTION><A NAME="05"></A><B>Graphics Mode Register (Index 05h)</B></CAPTION>
310 <TR ALIGN=CENTER VALIGN=CENTER>
311 <TD WIDTH="75">7</TD>
313 <TD WIDTH="75">6</TD>
315 <TD WIDTH="75">5</TD>
317 <TD WIDTH="75">4</TD>
319 <TD WIDTH="75">3</TD>
321 <TD WIDTH="75">2</TD>
323 <TD WIDTH="75">1</TD>
325 <TD WIDTH="75">0</TD>
328 <TR ALIGN=CENTER VALIGN=CENTER>
331 <TD WIDTH="75">Shift256</TD>
335 <TD WIDTH="75">Host O/E</TD>
337 <TD WIDTH="75">Read Mode</TD>
341 <TD COLSPAN="2" WIDTH="150">Write Mode</TD>
347 <B>Shift256 -- 256-Color Shift Mode<BR>
348 </B>"<I>When set to 0, this bit allows bit 5 to control the loading of
349 the shift registers. When set to 1, this bit causes the shift registers
350 to be loaded in a manner that supports the 256-color mode.</I>"</LI>
352 <BR><B>Shift Reg. -- Shift Register Interleave Mode<BR>
353 </B>"<I>When set to 1, this bit directs the shift registers in the graphics
354 controller to format the serial data stream with even-numbered bits from
355 both maps on even-numbered maps, and odd-numbered bits from both maps on
356 the odd-numbered maps. This bit is used for modes 4 and 5.</I>"
357 <BR><B>Host O/E -- Host Odd/Even Memory Read Addressing Enable<BR>
358 </B>"<I>When set to 1, this bit selects the odd/even addressing mode used
359 by the IBM Color/Graphics Monitor Adapter. Normally, the value here follows
360 the value of Memory Mode register bit 2 in the sequencer.</I>"
362 <B>Read Mode</B></LI>
364 <BR>This field selects between two read modes, simply known as Read Mode
365 0, and Read Mode 1, based upon the value of this field:
368 0b -- Read Mode 0: In this mode, a byte from one of the four planes is
369 returned on read operations. The plane from which the data is returned
370 is determined by the value of the <A HREF="#04">Read Map Select</A> field.</LI>
374 1b -- Read Mode 1: In this mode, a comparison is made between display memory
375 and a reference color defined by the <A HREF="#02">Color Compare</A> field.
376 Bit planes not set in the <A HREF="#07">Color Don't Care</A> field then
377 the corresponding color plane is not considered in the comparison. Each
378 bit in the returned result represents one comparison between the reference
379 color, with the bit being set if the comparison is true.</LI>
382 <B>Write Mode</B></LI>
384 <BR>This field selects between four write modes, simply known as Write
385 Modes 0-3, based upon the value of this field:
388 00b -- Write Mode 0: In this mode, the host data is first rotated as per
389 the <A HREF="#03">Rotate Count</A> field, then the <A HREF="#01">Enable
390 Set/Reset</A> mechanism selects data from this or the <A HREF="#00">Set/Reset</A>
391 field. Then the selected <A HREF="#03">Logical Operation</A> is performed
392 on the resulting data and the data in the latch register. Then the <A HREF="#08">Bit
393 Mask</A> field is used to select which bits come from the resulting data
394 and which come from the latch register. Finally, only the bit planes enabled
395 by the <A HREF="seqreg.htm#02">Memory Plane Write Enable</A> field are
396 written to memory.</LI>
399 01b -- Write Mode 1: In this mode, data is transferred directly from the
400 32 bit latch register to display memory, affected only by the <A HREF="seqreg.htm#02">Memory
401 Plane Write Enable</A> field. The host data is not used in this mode.</LI>
404 10b -- Write Mode 2: In this mode, the bits 3-0 of the host data are replicated
405 across all 8 bits of their respective planes. Then the selected <A HREF="#03">Logical
406 Operation</A> is performed on the resulting data and the data in the latch
407 register. Then the <A HREF="#08">Bit Mask</A> field is used to select which
408 bits come from the resulting data and which come from the latch register.
409 Finally, only the bit planes enabled by the <A HREF="seqreg.htm#02">Memory
410 Plane Write Enable</A> field are written to memory.</LI>
413 11b -- Write Mode 3: In this mode, the data in the <A HREF="#00">Set/Reset</A>
414 field is used as if the <A HREF="#01">Enable Set/Reset</A> field were set
415 to 1111b. Then the host data is first rotated as per the <A HREF="#03">Rotate
416 Count</A> field, then logical ANDed with the value of the <A HREF="#08">Bit
417 Mask</A> field. The resulting value is used on the data obtained from the
418 Set/Reset field in the same way that the <A HREF="#08">Bit Mask</A> field
419 would ordinarily be used. to select which bits come from the expansion
420 of the <A HREF="#00">Set/Reset</A> field and which come from the latch
421 register. Finally, only the bit planes enabled by the <A HREF="seqreg.htm#02">Memory
422 Plane Write Enable</A> field are written to memory.</LI>
426 <TABLE BORDER WIDTH="600" CELLPADING="2" >
427 <CAPTION ALIGN=TOP><A NAME="06"></A><B>Miscellaneous Graphics Register
428 (Index 06h)</B></CAPTION>
430 <TR ALIGN=CENTER VALIGN=CENTER>
431 <TD WIDTH="75">7</TD>
433 <TD WIDTH="75">6</TD>
435 <TD WIDTH="75">5</TD>
437 <TD WIDTH="75">4</TD>
439 <TD WIDTH="75">3</TD>
441 <TD WIDTH="75">2</TD>
443 <TD WIDTH="75">1</TD>
445 <TD WIDTH="75">0</TD>
448 <TR ALIGN=CENTER VALIGN=CENTER>
457 <TD COLSPAN="2" WIDTH="150">Memory Map Select</TD>
459 <TD WIDTH="75">Chain O/E</TD>
461 <TD WIDTH="75">Alpha Dis.</TD>
467 <B>Memory Map Select<BR>
468 </B>This field specifies the range of host memory addresses that is decoded
469 by the VGA hardware and mapped into display memory accesses. The
470 values of this field and their corresponding host memory ranges are:</LI>
474 00b -- A0000h-BFFFFh (128K region)</LI>
477 01b -- A0000h-AFFFFh (64K region)</LI>
480 10b -- B0000h-B7FFFh (32K region)</LI>
483 11b -- B8000h-BFFFFh (32K region)</LI>
485 <B>Chain O/E -- Chain Odd/Even Enable<BR>
486 </B>"<I>When set to 1, this bit directs the system address bit, A0, to
487 be replaced by a higher-order bit. The odd map is then selected when A0
488 is 1, and the even map when A0 is 0.</I>"
489 <BR><B>Alpha Dis. -- Alphanumeric Mode Disable<BR>
490 </B>"<I>This bit controls alphanumeric mode addressing. When set to 1,
491 this bit selects graphics modes, which also disables the character generator
494 <TABLE BORDER WIDTH="600" CELLPADING="2" >
495 <CAPTION ALIGN=TOP><A NAME="07"></A><B>Color Don't Care Register (Index
498 <TR ALIGN=CENTER VALIGN=CENTER>
499 <TD WIDTH="75">7</TD>
501 <TD WIDTH="75">6</TD>
503 <TD WIDTH="75">5</TD>
505 <TD WIDTH="75">4</TD>
507 <TD WIDTH="75">3</TD>
509 <TD WIDTH="75">2</TD>
511 <TD WIDTH="75">1</TD>
513 <TD WIDTH="75">0</TD>
516 <TR ALIGN=CENTER VALIGN=CENTER>
525 <TD COLSPAN="4" WIDTH="300">Color Don't Care</TD>
531 <B>Color Don't Care</B></LI>
533 <BR>Bits 3-0 of this field represent planes 3-0 of the VGA display memory.
534 This field selects the planes that are used in the comparisons made by
535 Read Mode 1 (See the <A HREF="#05">Read Mode</A> field.) Read Mode 1 returns
536 the result of the comparison between the value of the <A HREF="#02">Color
537 Compare</A> field and a location of display memory. If a bit in this field
538 is set, then the corresponding display plane is considered in the comparison.
539 If it is not set, then that plane is ignored for the results of the comparison.</UL>
541 <TABLE BORDER WIDTH="600" CELLPADING="2" >
542 <CAPTION ALIGN=TOP><A NAME="08"></A><B>Bit Mask Register (Index 08h)</B></CAPTION>
544 <TR ALIGN=CENTER VALIGN=CENTER>
545 <TD WIDTH="75">7</TD>
547 <TD WIDTH="75">6</TD>
549 <TD WIDTH="75">5</TD>
551 <TD WIDTH="75">4</TD>
553 <TD WIDTH="75">3</TD>
555 <TD WIDTH="75">2</TD>
557 <TD WIDTH="75">1</TD>
559 <TD WIDTH="75">0</TD>
562 <TR ALIGN=CENTER VALIGN=CENTER>
563 <TD COLSPAN="8" WIDTH="600">Bit Mask</TD>
571 <BR>This field is used in Write Modes 0, 2, and 3 (See the <A HREF="#05">Write
572 Mode</A> field.) It it is applied to one byte of data in all four display
573 planes. If a bit is set, then the value of corresponding bit from the previous
574 stage in the graphics pipeline is selected; otherwise the value of the
575 corresponding bit in the latch register is used instead. In Write Mode
576 3, the incoming data byte, after being rotated is logical ANDed with this
577 byte and the resulting value is used in the same way this field would normally
578 be used by itself.</UL>
579 Notice: All trademarks used or referred to on this page are the property
580 of their respective owners.
581 <BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
582 noted. Permission for utilization and distribution is subject to the terms
583 of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.