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5 <META NAME="Description" CONTENT="Pure VGA/SVGA hardware programming (registers, identification, and other low-level stuff.)">
6 <META NAME="KeyWords" CONTENT="VGA SVGA hardware video programming">
7 <TITLE>VGA/SVGA Video Programming--Color Regsters</TITLE>
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13 <HR WIDTH="100%"><B>Hardware Level VGA and SVGA Video Programming Information
16 <CENTER>Color Registers</CENTER>
19 <HR WIDTH="100%"></CENTER>
21 The Color Registers in the standard
22 VGA provide a mapping between the palette of between 2 and 256 colors to
23 a larger 18-bit color space. This capability allows for efficient use of
24 video memory while providing greater flexibility in color choice. The standard
25 VGA has 256 palette entries containing six bits each of red, green, and
26 blue values. The palette RAM is accessed via a pair of address registers
27 and a data register. To write a palette entry, output the palette entry's
28 index value to the <A HREF="#3C8">DAC Address Write Mode Register</A> then
29 perform 3 writes to the <A HREF="#3C9">DAC Data Register</A>, loading the
30 red, green, then blue values into the palette RAM. The internal write address
31 automatically advances allowing the next value's RGB values to be loaded
32 without having to reprogram the <A HREF="#3C8">DAC Address Write Mode Register.
33 This</A> allows the entire palette to be loaded in one write operation.
34 To read a palette entry, output the palette entry's index to the <A HREF="#3C7W">DAC
35 Address Read Mode Register</A>. Then perform 3 reads from the <A HREF="#3C9">DAC
36 Data Register</A>, loading the red, green, then blue values from palette
37 RAM. The internal write address automatically advances allowing the next
38 RGB values to be written without having to reprogram the <A HREF="#3C7W">DAC
39 Address Read Mode Register</A>.
41 <P><A NAME="note"></A>Note: I have noticed some great variance in the actual
42 behavior of these registers on VGA chipsets. The best way to ensure compatibility
43 with the widest range of cards is to start an operation by writing to the
44 appropriate address register and performing reads and writes in groups
45 of 3 color values. While the automatic increment works fine on all cards
46 tested, reading back the value from the <A HREF="#3C8">DAC Address Write
47 Mode Register</A> may not always produce the expected result. Also interleaving
48 reads and writes to the <A HREF="#3C9">DAC Data Register</A> without first
49 writing to the respected address register may produce unexpected results.
50 In addition, writing values in anything other than groups of 3 to the <A HREF="#3C9">DAC
51 Data Register</A> and then performing reads may produce unexpected results.
52 I have found that some cards fail to perform the desired update until the
53 third value is written.
56 Port 3C8h -- <A HREF="#3C8">DAC Address Write Mode Register</A></LI>
59 Port 3C7h -- <A HREF="#3C7W">DAC Address Read Mode Register</A></LI>
62 Port 3C9h -- <A HREF="#3C9">DAC Data Register</A></LI>
65 Port 3C7h -- <A HREF="#3C7R">DAC State Register</A></LI>
68 <TABLE BORDER WIDTH="600" CELLPADING="2" >
69 <CAPTION ALIGN=TOP><A NAME="3C8"></A><B>DAC Address Write Mode Register
70 (Read/Write at 3C8h)</B></CAPTION>
72 <TR ALIGN=CENTER VALIGN=CENTER>
90 <TR ALIGN=CENTER VALIGN=CENTER>
91 <TD COLSPAN="8" WIDTH="600">DAC Write Address</TD>
97 <B>DAC Write Address</B></LI>
99 <BR>Writing to this register prepares the DAC hardware to accept writes
100 of data to the <A HREF="#3C9">DAC Data Register</A>. The value written
101 is the index of the first DAC entry to be written (multiple DAC entries
102 may be written without having to reset the write address due to the auto-increment.)
103 Reading this register returns the current index, or at least theoretically
104 it should. However it is likely the value returned is not the one expected,
105 and is dependent on the particular DAC implementation. (See <A HREF="#note">note</A>
108 <TABLE BORDER WIDTH="600" CELLPADING="2" >
109 <CAPTION ALIGN=TOP><A NAME="3C7W"></A><B>DAC Address Read Mode Register
110 (Write at 3C7h)</B></CAPTION>
112 <TR ALIGN=CENTER VALIGN=CENTER>
113 <TD WIDTH="75">7</TD>
115 <TD WIDTH="75">6</TD>
117 <TD WIDTH="75">5</TD>
119 <TD WIDTH="75">4</TD>
121 <TD WIDTH="75">3</TD>
123 <TD WIDTH="75">2</TD>
125 <TD WIDTH="75">1</TD>
127 <TD WIDTH="75">0</TD>
130 <TR ALIGN=CENTER VALIGN=CENTER>
131 <TD COLSPAN="8" WIDTH="600">DAC Read Address</TD>
137 <B>DAC Read Address</B></LI>
139 <BR>Writing to this register prepares the DAC hardware to accept reads
140 of data to the <A HREF="#3C9">DAC Data Register</A>. The value written
141 is the index of the first DAC entry to be read (multiple DAC entries may
142 be read without having to reset the write address due to the auto-increment.)</UL>
144 <TABLE BORDER WIDTH="600" CELLPADING="2" >
145 <CAPTION ALIGN=TOP><A NAME="3C9"></A><B>DAC Data Register (Read/Write at
148 <TR ALIGN=CENTER VALIGN=CENTER>
149 <TD WIDTH="75">7</TD>
151 <TD WIDTH="75">6</TD>
153 <TD WIDTH="75">5</TD>
155 <TD WIDTH="75">4</TD>
157 <TD WIDTH="75">3</TD>
159 <TD WIDTH="75">2</TD>
161 <TD WIDTH="75">1</TD>
163 <TD WIDTH="75">0</TD>
166 <TR ALIGN=CENTER VALIGN=CENTER>
171 <TD COLSPAN="6" WIDTH="450">DAC Data</TD>
179 <BR>Reading or writing to this register returns a value from the DAC memory.
180 Three successive I/O operations accesses three intensity values, first
181 the red, then green, then blue intensity values. The index of the DAC entry
182 accessed is initially specified by the <A HREF="#3C7W">DAC Address Read
183 Mode Register</A> or the <A HREF="#3C8">DAC Address Write Mode Register</A>,
184 depending on the I/O operation performed. After three I/O operations the
185 index automatically increments to allow the next DAC entry to be read without
186 having to reload the index. I/O operations to this port should always be
187 performed in sets of three, otherwise the results are dependent on the
188 DAC implementation. (See <A HREF="#note">note</A> above)</UL>
190 <TABLE BORDER WIDTH="600" CELLPADING="2" >
191 <CAPTION ALIGN=TOP><A NAME="3C7R"></A><B>DAC State Register (Read at 3C7h)</B></CAPTION>
193 <TR ALIGN=CENTER VALIGN=CENTER>
194 <TD WIDTH="75">7</TD>
196 <TD WIDTH="75">6</TD>
198 <TD WIDTH="75">5</TD>
200 <TD WIDTH="75">4</TD>
202 <TD WIDTH="75">3</TD>
204 <TD WIDTH="75">2</TD>
206 <TD WIDTH="75">1</TD>
208 <TD WIDTH="75">0</TD>
211 <TR ALIGN=CENTER VALIGN=CENTER>
224 <TD COLSPAN="2" WIDTH="150">DAC State</TD>
230 <B>DAC State</B></LI>
232 <BR>This field returns whether the DAC is prepared to accept reads or writes
233 to the <A HREF="#3C9">DAC Data Register</A>. In practice, this field is
234 seldom used due to the DAC state being known after the index has been written.
235 This field can have the following values:
238 00 -- DAC is prepared to accept reads from the <A HREF="#3C9">DAC Data
242 11 -- DAC is prepared to accept writes to the <A HREF="#3C9">DAC Data Register</A>.</LI>
247 <P>Notice: All trademarks used or referred to on this page are the property
248 of their respective owners.
249 <BR>All pages are Copyright © 1997, 1998, J. D. Neal, except where
250 noted. Permission for utilization and distribution is subject to the terms
251 of the <A HREF="license.htm">FreeVGA Project Copyright License</A>.