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+ VGA/SVGA Video Programming--Color Regsters
+
+
+
+
+Home Back
+
Hardware Level VGA and SVGA Video Programming Information
+Page
+
+Color Registers
+
+
+
+
+ The Color Registers in the standard
+VGA provide a mapping between the palette of between 2 and 256 colors to
+a larger 18-bit color space. This capability allows for efficient use of
+video memory while providing greater flexibility in color choice. The standard
+VGA has 256 palette entries containing six bits each of red, green, and
+blue values. The palette RAM is accessed via a pair of address registers
+and a data register. To write a palette entry, output the palette entry's
+index value to the DAC Address Write Mode Register then
+perform 3 writes to the DAC Data Register, loading the
+red, green, then blue values into the palette RAM. The internal write address
+automatically advances allowing the next value's RGB values to be loaded
+without having to reprogram the DAC Address Write Mode Register.
+This allows the entire palette to be loaded in one write operation.
+To read a palette entry, output the palette entry's index to the DAC
+Address Read Mode Register. Then perform 3 reads from the DAC
+Data Register, loading the red, green, then blue values from palette
+RAM. The internal write address automatically advances allowing the next
+RGB values to be written without having to reprogram the DAC
+Address Read Mode Register.
+
+Note: I have noticed some great variance in the actual
+behavior of these registers on VGA chipsets. The best way to ensure compatibility
+with the widest range of cards is to start an operation by writing to the
+appropriate address register and performing reads and writes in groups
+of 3 color values. While the automatic increment works fine on all cards
+tested, reading back the value from the DAC Address Write
+Mode Register may not always produce the expected result. Also interleaving
+reads and writes to the DAC Data Register without first
+writing to the respected address register may produce unexpected results.
+In addition, writing values in anything other than groups of 3 to the DAC
+Data Register and then performing reads may produce unexpected results.
+I have found that some cards fail to perform the desired update until the
+third value is written.
+
+
+
+DAC Address Write Mode Register
+(Read/Write at 3C8h)
+
+
+| 7 |
+
+6 |
+
+5 |
+
+4 |
+
+3 |
+
+2 |
+
+1 |
+
+0 |
+
+
+
+| DAC Write Address |
+
+
+
+
+-
+DAC Write Address
+
+
Writing to this register prepares the DAC hardware to accept writes
+of data to the DAC Data Register. The value written
+is the index of the first DAC entry to be written (multiple DAC entries
+may be written without having to reset the write address due to the auto-increment.)
+Reading this register returns the current index, or at least theoretically
+it should. However it is likely the value returned is not the one expected,
+and is dependent on the particular DAC implementation. (See note
+above)
+
+
+DAC Address Read Mode Register
+(Write at 3C7h)
+
+
+| 7 |
+
+6 |
+
+5 |
+
+4 |
+
+3 |
+
+2 |
+
+1 |
+
+0 |
+
+
+
+| DAC Read Address |
+
+
+
+
+-
+DAC Read Address
+
+
Writing to this register prepares the DAC hardware to accept reads
+of data to the DAC Data Register. The value written
+is the index of the first DAC entry to be read (multiple DAC entries may
+be read without having to reset the write address due to the auto-increment.)
+
+
+DAC Data Register (Read/Write at
+3C9h)
+
+
+| 7 |
+
+6 |
+
+5 |
+
+4 |
+
+3 |
+
+2 |
+
+1 |
+
+0 |
+
+
+
+ |
+
+ |
+
+DAC Data |
+
+
+
+
+-
+DAC Data
+
+
Reading or writing to this register returns a value from the DAC memory.
+Three successive I/O operations accesses three intensity values, first
+the red, then green, then blue intensity values. The index of the DAC entry
+accessed is initially specified by the DAC Address Read
+Mode Register or the DAC Address Write Mode Register,
+depending on the I/O operation performed. After three I/O operations the
+index automatically increments to allow the next DAC entry to be read without
+having to reload the index. I/O operations to this port should always be
+performed in sets of three, otherwise the results are dependent on the
+DAC implementation. (See note above)
+
+
+DAC State Register (Read at 3C7h)
+
+
+| 7 |
+
+6 |
+
+5 |
+
+4 |
+
+3 |
+
+2 |
+
+1 |
+
+0 |
+
+
+
+ |
+
+ |
+
+ |
+
+ |
+
+ |
+
+ |
+
+DAC State |
+
+
+
+
+-
+DAC State
+
+
This field returns whether the DAC is prepared to accept reads or writes
+to the DAC Data Register. In practice, this field is
+seldom used due to the DAC state being known after the index has been written.
+This field can have the following values:
+
+
+
+
+Notice: All trademarks used or referred to on this page are the property
+of their respective owners.
+
All pages are Copyright © 1997, 1998, J. D. Neal, except where
+noted. Permission for utilization and distribution is subject to the terms
+of the FreeVGA Project Copyright License.
+
+