From 8abbb333aea445641d967befd3ca477502ea770b Mon Sep 17 00:00:00 2001 From: Ben Pfaff Date: Sun, 29 Jan 2006 21:32:55 +0000 Subject: [PATCH] Update Intel architecture guide references to latest. Thanks to Josh Wiseman and Godmar Back for pointing this out. --- doc/references.texi | 36 +++++++++++++++++++----------------- doc/standards.texi | 2 +- doc/threads.texi | 4 ++-- doc/tour.texi | 18 ++++++++++-------- doc/vm.texi | 5 +++-- src/threads/init.c | 3 ++- src/threads/interrupt.c | 29 ++++++++++++++++++++--------- src/threads/loader.S | 7 +++++-- src/threads/mmu.h | 3 ++- src/threads/thread.c | 3 ++- src/userprog/exception.c | 8 ++++---- src/userprog/gdt.c | 11 +++++++---- src/userprog/pagedir.c | 11 ++++++----- src/userprog/tss.c | 7 ++++--- 14 files changed, 87 insertions(+), 60 deletions(-) diff --git a/doc/references.texi b/doc/references.texi index 78c6b8c..2a3b8d2 100644 --- a/doc/references.texi +++ b/doc/references.texi @@ -16,28 +16,30 @@ @section Hardware References @bibdfn{IA32-v1} -@uref{ftp://download.intel.com/design/Pentium4/manuals/25366515.pdf, , IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic -Architecture}. Basic 80@var{x}86 architecture and programming -environment. +Architecture. Basic 80@var{x}86 architecture and programming +environment. Available via @uref{developer.intel.com}. Section numbers +in this document refer to revision 18. -@bibdfn{IA32-v2a} -@uref{ftp://download.intel.com/design/Pentium4/manuals/25366615.pdf, , -IA-32 Intel Architecture Software Developer's Manual Volume 2A: -Instruction Set Reference A-M}. 80@var{x}86 instructions whose names -begin with A through M. +@bibdfn{IA32-v2a} +IA-32 Intel Architecture Software Developer's Manual +Volume 2A: Instruction Set Reference A-M. 80@var{x}86 instructions +whose names begin with A through M. Available via +@uref{developer.intel.com}. Section numbers in this document refer to +revision 18. @bibdfn{IA32-v2b} -@uref{ftp://download.intel.com/design/Pentium4/manuals/25366715.pdf, , IA-32 Intel Architecture Software Developer's Manual Volume 2B: -Instruction Set Reference N-Z}. 80@var{x}86 instructions whose names -begin with N through Z. - -@bibdfn{IA32-v3} -@uref{ftp://download.intel.com/design/Pentium4/manuals/25366815.pdf, , -IA-32 Intel Architecture Software Developer's Manual Volume 3: System -Programming Guide}. Operating system support, including segmentation, -paging, tasks, interrupt and exception handling. +Instruction Set Reference N-Z. 80@var{x}86 instructions whose names +begin with N through Z. Available via @uref{developer.intel.com}. +Section numbers in this document refer to revision 18. + +@bibdfn{IA32-v3a} +IA-32 Intel Architecture Software Developer's Manual Volume 3A: System +Programming Guide. Operating system support, including segmentation, +paging, tasks, interrupt and exception handling. Available via +@uref{developer.intel.com}. Section numbers in this document refer to +revision 18. @bibdfn{FreeVGA} @uref{specs/freevga/home.htm, , FreeVGA Project}. Documents the VGA video diff --git a/doc/standards.texi b/doc/standards.texi index fbd673a..8e0f0e0 100644 --- a/doc/standards.texi +++ b/doc/standards.texi @@ -44,7 +44,7 @@ Please limit C source file lines to at most 79 characters long. Pintos comments sometimes refer to external standards or specifications by writing a name inside square brackets, like this: -@code{[IA32-v3]}. These names refer to the reference names used in +@code{[IA32-v3a]}. These names refer to the reference names used in this documentation (@pxref{References}). If you remove existing Pintos code, please delete it from your source diff --git a/doc/threads.texi b/doc/threads.texi index b84a8f6..8f07bb7 100644 --- a/doc/threads.texi +++ b/doc/threads.texi @@ -185,8 +185,8 @@ project 3. For now, you can ignore it. @item flags.h Macros that define a few bits in the 80@var{x}86 ``flags'' register. -Probably of no interest. See @bibref{IA32-v1}, section 3.4.3, for more -information. +Probably of no interest. See @bibref{IA32-v1}, section 3.4.3, ``EFLAGS +Register,'' for more information. @end table @menu diff --git a/doc/tour.texi b/doc/tour.texi index 750145b..c0568f1 100644 --- a/doc/tour.texi +++ b/doc/tour.texi @@ -41,8 +41,8 @@ the rest of Pintos into memory, and then jumping to its start. It's not important to understand exactly what the loader does, but if you're interested, read on. You should probably read along with the loader's source. You should also understand the basics of the -80@var{x}86 architecture as described by chapter 3 of -@bibref{IA32-v1}. +80@var{x}86 architecture as described by chapter 3, ``Basic Execution +Environment,'' of @bibref{IA32-v1}. Because the PC BIOS loads the loader, the loader has to play by the BIOS's rules. In particular, the BIOS only loads 512 bytes (one disk @@ -934,9 +934,10 @@ external interrupts, to a point. The following section describes this common infrastructure, and sections after that give the specifics of external and internal interrupts. -If you haven't already read chapter 3 in @bibref{IA32-v1}, it is -recommended that you do so now. You might also want to skim chapter 5 -in @bibref{IA32-v3}. +If you haven't already read chapter 3, ``Basic Execution Environment,'' +in @bibref{IA32-v1}, it is recommended that you do so now. You might +also want to skim chapter 5, ``Interrupt and Exception Handling,'' in +@bibref{IA32-v3a}. @menu * Interrupt Infrastructure:: @@ -1300,9 +1301,10 @@ Most implementations of the virtual memory project use a hash table to translate virtual page frames to physical page frames. It is possible to do this translation without adding a new data structure, by modifying the code in @file{userprog/pagedir.c}. However, if you do that you'll -need to carefully study and understand section 3.7 in @bibref{IA32-v3}, -and in practice it is probably easier to add a new data structure. You -may find other uses for hash tables as well. +need to carefully study and understand section 3.7, ``Page Translation +Using 32-Bit Physical Addressing,'' in @bibref{IA32-v3a}, and in practice +it is probably easier to add a new data structure. You may find other +uses for hash tables as well. Pintos provides a hash table data structure in @file{lib/kernel/hash.c}. To use it you will need to manually include its header file, diff --git a/doc/vm.texi b/doc/vm.texi index 6e5d5a0..840e506 100644 --- a/doc/vm.texi +++ b/doc/vm.texi @@ -318,8 +318,9 @@ useful for this purpose (@pxref{Hash Table}). It is possible to do this translation without adding a new data structure, by modifying the code in @file{userprog/pagedir.c}. However, -if you do that you'll need to carefully study and understand section 3.7 -in @bibref{IA32-v3}, and in practice it is probably easier to add a new +if you do that you'll need to carefully study and understand section +3.7, ``Page Translation Using 32-Bit Physical Addressing,'' in +@bibref{IA32-v3a}, and in practice it is probably easier to add a new data structure. @item diff --git a/src/threads/init.c b/src/threads/init.c index c6917e2..cb4edf9 100644 --- a/src/threads/init.c +++ b/src/threads/init.c @@ -188,7 +188,8 @@ paging_init (void) /* Store the physical address of the page directory into CR3 aka PDBR (page directory base register). This activates our new page tables immediately. See [IA32-v2a] "MOV--Move - to/from Control Registers" and [IA32-v3] 3.7.5. */ + to/from Control Registers" and [IA32-v3a] 3.7.5 "Base Address + of the Page Directory". */ asm volatile ("movl %0, %%cr3" :: "r" (vtop (base_page_dir))); } diff --git a/src/threads/interrupt.c b/src/threads/interrupt.c index 2b43fd9..29aea87 100644 --- a/src/threads/interrupt.c +++ b/src/threads/interrupt.c @@ -14,7 +14,9 @@ #define INTR_CNT 256 /* The Interrupt Descriptor Table (IDT). The format is fixed by - the CPU. See [IA32-v3] sections 5.10, 5.11, 5.12.1.2. */ + the CPU. See [IA32-v3a] sections 5.10 "Interrupt Descriptor + Table (IDT)", 5.11 "IDT Descriptors", 5.12.1.2 "Flag Usage By + Exception- or Interrupt-Handler Procedure". */ static uint64_t idt[INTR_CNT]; /* Interrupt handler functions for each interrupt. */ @@ -53,7 +55,8 @@ intr_get_level (void) /* Push the flags register on the processor stack, then pop the value off the stack into `flags'. See [IA32-v2b] "PUSHF" - and "POP" and [IA32-v3] 5.8.1. */ + and "POP" and [IA32-v3a] 5.8.1 "Masking Maskable Hardware + Interrupts". */ asm volatile ("pushfl; popl %0" : "=g" (flags)); return flags & FLAG_IF ? INTR_ON : INTR_OFF; @@ -75,7 +78,9 @@ intr_enable (void) ASSERT (!intr_context ()); /* Enable interrupts by setting the interrupt flag. - See [IA32-v2b] "STI" and [IA32-v3] 5.8.1. */ + + See [IA32-v2b] "STI" and [IA32-v3a] 5.8.1 "Masking Maskable + Hardware Interrupts". */ asm volatile ("sti"); return old_level; @@ -88,7 +93,8 @@ intr_disable (void) enum intr_level old_level = intr_get_level (); /* Disable interrupts by clearing the interrupt flag. - See [IA32-v2b] "CLI" and [IA32-v3] 5.8.1. */ + See [IA32-v2b] "CLI" and [IA32-v3a] 5.8.1 "Masking Maskable + Hardware Interrupts". */ asm volatile ("cli"); return old_level; @@ -109,7 +115,8 @@ intr_init (void) idt[i] = make_intr_gate (intr_stubs[i], 0); /* Load IDT register. - See [IA32-v2a] "LIDT" and [IA32-v3] 5.10. */ + See [IA32-v2a] "LIDT" and [IA32-v3a] 5.10 "Interrupt + Descriptor Table (IDT)". */ idtr_operand = make_idtr_operand (sizeof idt - 1, idt); asm volatile ("lidt %0" :: "m" (idtr_operand)); @@ -175,7 +182,9 @@ intr_register_ext (uint8_t vec_no, intr_handler_func *handler, user mode to invoke the interrupts and DPL==0 prevents such invocation. Faults and exceptions that occur in user mode still cause interrupts with DPL==0 to be invoked. See - [IA32-v3] sections 4.5 and 4.8.1.1 for further discussion. */ + [IA32-v3a] sections 4.5 "Privilege Levels" and 4.8.1.1 + "Accessing Nonconforming Code Segments" for further + discussion. */ void intr_register_int (uint8_t vec_no, int dpl, enum intr_level level, intr_handler_func *handler, const char *name) @@ -266,13 +275,15 @@ pic_end_of_interrupt (int irq) or lower-numbered ring. In practice, DPL==3 allows user mode to call into the gate and DPL==0 prevents such calls. Faults and exceptions that occur in user mode still cause gates with - DPL==0 to be invoked. See [IA32-v3] sections 4.5 and 4.8.1.1 + DPL==0 to be invoked. See [IA32-v3a] sections 4.5 "Privilege + Levels" and 4.8.1.1 "Accessing Nonconforming Code Segments" for further discussion. TYPE must be either 14 (for an interrupt gate) or 15 (for a trap gate). The difference is that entering an interrupt gate disables interrupts, but entering a trap gate does not. See - [IA32-v3] section 5.12.1.2 for discussion. */ + [IA32-v3a] section 5.12.1.2 "Flag Usage By Exception- or + Interrupt-Handler Procedure" for discussion. */ static uint64_t make_gate (void (*function) (void), int dpl, int type) { @@ -378,7 +389,7 @@ intr_dump_frame (const struct intr_frame *f) /* Store current value of CR2 into `cr2'. CR2 is the linear address of the last page fault. See [IA32-v2a] "MOV--Move to/from Control Registers" and - [IA32-v3] 5.14 "Interrupt 14--Page Fault Exception + [IA32-v3a] 5.14 "Interrupt 14--Page Fault Exception (#PF)". */ asm ("movl %%cr2, %0" : "=r" (cr2)); diff --git a/src/threads/loader.S b/src/threads/loader.S index fc834ff..2d76763 100644 --- a/src/threads/loader.S +++ b/src/threads/loader.S @@ -138,7 +138,9 @@ start: # Add PDEs to point to PTEs for the first 64 MB of RAM. # Also add identical PDEs starting at LOADER_PHYS_BASE. -# See [IA32-v3] section 3.7.6 for a description of the bits in %eax. +# See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries" +# for a description of the bits in %eax. + movl $0x11007, %eax movl $0x11, %ecx @@ -150,7 +152,8 @@ start: loop 1b # Set up one-to-map linear to physical map for the first 64 MB of RAM. -# See [IA32-v3] section 3.7.6 for a description of the bits in %eax. +# See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries" +# for a description of the bits in %eax. movw $0x1100, %ax movw %ax, %es diff --git a/src/threads/mmu.h b/src/threads/mmu.h index 6f8741c..e635b1e 100644 --- a/src/threads/mmu.h +++ b/src/threads/mmu.h @@ -142,7 +142,8 @@ vtop (const void *vaddr) /* Page directories and page tables. - For more information see [IA32-v3] pages 3-23 to 3-28. + For more information see [IA32-v3a] 3.7.6 "Page-Directory and + Page-Table Entries". PDEs and PTEs share a common format: diff --git a/src/threads/thread.c b/src/threads/thread.c index 5229aef..01e8ea4 100644 --- a/src/threads/thread.c +++ b/src/threads/thread.c @@ -365,7 +365,8 @@ idle (void *aux UNUSED) one to occur, wasting as much as one clock tick worth of time. - See [IA32-v2a] "HLT", [IA32-v2b] "STI", and [IA32-v3] 7.7. */ + See [IA32-v2a] "HLT", [IA32-v2b] "STI", and [IA32-v3a] + 7.11.1 "HLT Instruction". */ asm ("sti; hlt"); } } diff --git a/src/userprog/exception.c b/src/userprog/exception.c index 985cd17..19aca12 100644 --- a/src/userprog/exception.c +++ b/src/userprog/exception.c @@ -24,8 +24,8 @@ static void page_fault (struct intr_frame *); way as other exceptions, but this will need to change to implement virtual memory. - Refer to [IA32-v3] section 5.14 for a description of each of - these exceptions. */ + Refer to [IA32-v3a] section 5.15 "Exception and Interrupt + Reference" for a description of each of these exceptions. */ void exception_init (void) { @@ -118,7 +118,7 @@ kill (struct intr_frame *f) example code here shows how to parse that information. You can find more information about both of these in the description of "Interrupt 14--Page Fault Exception (#PF)" in - [IA32-v3] section 5.14, which is pages 5-46 to 5-49. */ + [IA32-v3a] section 5.15 "Exception and Interrupt Reference". */ static void page_fault (struct intr_frame *f) { @@ -132,7 +132,7 @@ page_fault (struct intr_frame *f) data. It is not necessarily the address of the instruction that caused the fault (that's f->eip). See [IA32-v2a] "MOV--Move to/from Control Registers" and - [IA32-v3] 5.14 "Interrupt 14--Page Fault Exception + [IA32-v3a] 5.15 "Interrupt 14--Page Fault Exception (#PF)". */ asm ("movl %%cr2, %0" : "=r" (fault_addr)); diff --git a/src/userprog/gdt.c b/src/userprog/gdt.c index 42cad61..0e393ec 100644 --- a/src/userprog/gdt.c +++ b/src/userprog/gdt.c @@ -20,7 +20,8 @@ stack switching on interrupts. For more information on the GDT as used here, refer to - [IA32-v3] sections 3.2 through 3.5. */ + [IA32-v3a] 3.2 "Using Segments" through 3.5 "System Descriptor + Types". */ static uint64_t gdt[SEL_CNT]; /* GDT helpers. */ @@ -44,7 +45,9 @@ gdt_init (void) gdt[SEL_UDSEG / sizeof *gdt] = make_data_desc (3); gdt[SEL_TSS / sizeof *gdt] = make_tss_desc (tss_get ()); - /* Load GDTR, TR. See [IA32-v3] 2.4.1, 2.4.4, 6.2.3. */ + /* Load GDTR, TR. See [IA32-v3a] 2.4.1 "Global Descriptor + Table Register (GDTR)", 2.4.4 "Task Register (TR)", and + 6.2.4 "Task Register". */ gdtr_operand = make_gdtr_operand (sizeof gdt - 1, gdt); asm volatile ("lgdt %0" :: "m" (gdtr_operand)); asm volatile ("ltr %w0" :: "r" (SEL_TSS)); @@ -74,7 +77,7 @@ enum seg_granularity it can be used in rings numbered DPL or lower. In practice, DPL==3 means that user processes can use the segment and DPL==0 means that only the kernel can use the segment. See - [IA32-v3] section 4.5 for further discussion. */ + [IA32-v3a] 4.5 "Privilege Levels" for further discussion. */ static uint64_t make_seg_desc (uint32_t base, uint32_t limit, @@ -126,7 +129,7 @@ make_data_desc (int dpl) /* Returns a descriptor for an "available" 32-bit Task-State Segment with its base at the given linear address, a limit of 0x67 bytes (the size of a 32-bit TSS), and a DPL of 0. - See [IA32-v3] 6.2.2. */ + See [IA32-v3a] 6.2.2 "TSS Descriptor". */ static uint64_t make_tss_desc (void *laddr) { diff --git a/src/userprog/pagedir.c b/src/userprog/pagedir.c index 820755f..ea3c1f4 100644 --- a/src/userprog/pagedir.c +++ b/src/userprog/pagedir.c @@ -224,7 +224,8 @@ pagedir_activate (uint32_t *pd) /* Store the physical address of the page directory into CR3 aka PDBR (page directory base register). This activates our new page tables immediately. See [IA32-v2a] "MOV--Move - to/from Control Registers" and [IA32-v3] 3.7.5. */ + to/from Control Registers" and [IA32-v3a] 3.7.5 "Base + Address of the Page Directory". */ asm volatile ("movl %0, %%cr3" :: "r" (vtop (pd))); } @@ -235,7 +236,7 @@ active_pd (void) /* Copy CR3, the page directory base register (PDBR), into `pd'. See [IA32-v2a] "MOV--Move to/from Control Registers" and - [IA32-v3] 3.7.5. */ + [IA32-v3a] 3.7.5 "Base Address of the Page Directory". */ uintptr_t pd; asm volatile ("movl %%cr3, %0" : "=r" (pd)); return ptov (pd); @@ -254,9 +255,9 @@ invalidate_pagedir (uint32_t *pd) { if (active_pd () == pd) { - /* We cleared a page-table entry in the active page - table, so we have to invalidate the TLB. See - [IA32-v3], section 3.11. */ + /* We cleared a page-table entry in the active page table, + so we have to invalidate the TLB. See [IA32-v3a] 3.12 + "Translation Lookaside Buffers (TLBs)". */ pagedir_activate (pd); } } diff --git a/src/userprog/tss.c b/src/userprog/tss.c index cddad93..dfda3b9 100644 --- a/src/userprog/tss.c +++ b/src/userprog/tss.c @@ -43,9 +43,10 @@ stack pointer to point to the new thread's kernel stack. (The call is in schedule_tail() in thread.c.) - See [IA32-v3] 6.2.1 for a description of the TSS and 5.12.1 - for a description of when and how stack switching occurs - during an interrupt. */ + See [IA32-v3a] 6.2.1 "Task-State Segment (TSS)" for a + description of the TSS. See [IA32-v3a] 5.12.1 "Exception- or + Interrupt-Handler Procedures" for a description of when and + how stack switching occurs during an interrupt. */ struct tss { uint16_t back_link, :16; -- 2.30.2