From: Ben Pfaff <blp@cs.stanford.edu>
Date: Sun, 2 Jan 2005 02:09:58 +0000 (+0000)
Subject: Change assembly from AT&T to Intel syntax.
X-Git-Url: https://pintos-os.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=5b670fb86ef37f5a81188e940e5fe1b04b5824af;p=pintos-anon

Change assembly from AT&T to Intel syntax.
Update makefile.
Apply corresponding changes to the documentation,
the sample solutions, and the grading programs.
---

diff --git a/TODO b/TODO
index a07e2b4..15902a2 100644
--- a/TODO
+++ b/TODO
@@ -1,11 +1,5 @@
 -*- text -*-
 
-* Clean up:
-
-  - Replace AT&T assembly code by Intel assembly so that students can
-    figure out the asm from the Intel manuals.  Compare object files
-    before and after to make sure nothing changed.
-
 * Userprog project:
 
   - Move `join' implementation here, from `threads' project, to help
diff --git a/doc/userprog.texi b/doc/userprog.texi
index 884b757..a92697d 100644
--- a/doc/userprog.texi
+++ b/doc/userprog.texi
@@ -686,7 +686,7 @@ provide a little bit of helpful code:
    Returns true if successful, false if USRC is invalid. */
 static inline bool get_user (uint8_t *dst, const uint8_t *usrc) {
   int eax;
-  asm ("movl $1f, %%eax; movb %2, %%al; movb %%al, %0; 1:"
+  asm ("mov %%eax, offset 1f; mov %%al, %2; mov %0, %%al; 1:"
        : "=m" (*dst), "=&a" (eax) : "m" (*usrc));
   return eax != 0;
 }
@@ -695,7 +695,7 @@ static inline bool get_user (uint8_t *dst, const uint8_t *usrc) {
    Returns true if successful, false if UDST is invalid. */
 static inline bool put_user (uint8_t *udst, uint8_t byte) {
   int eax;
-  asm ("movl $1f, %%eax; movb %b2, %0; 1:"
+  asm ("mov %%eax, offset 1f; mov %0, %b2; 1:"
        : "=m" (*udst), "=&a" (eax) : "r" (byte));
   return eax != 0;
 }
diff --git a/grading/userprog/child-bad.c b/grading/userprog/child-bad.c
index 914bde6..97a9a3b 100644
--- a/grading/userprog/child-bad.c
+++ b/grading/userprog/child-bad.c
@@ -5,7 +5,7 @@ int
 main (void) 
 {
   printf ("(child-bad) begin\n"); 
-  asm volatile ("mov $0x20101234, %esp; int $0x30");
+  asm volatile ("mov %esp, 0x20101234; int 0x30");
   printf ("(child-bad) end\n"); 
   return 0;
 }
diff --git a/grading/userprog/sc-bad-arg.c b/grading/userprog/sc-bad-arg.c
index e6019a6..bfab37b 100644
--- a/grading/userprog/sc-bad-arg.c
+++ b/grading/userprog/sc-bad-arg.c
@@ -5,9 +5,8 @@ int
 main (void) 
 {
   printf ("(sc-bad-arg) begin\n"); 
-  asm volatile ("mov $0xbffffffc, %%esp; movl %0, (%%esp); int $0x30"
-                :
-                : "i" (SYS_exit));
+  asm volatile ("mov %%esp, 0xbffffffc; mov [dword ptr %%esp], %0; int 0x30"
+                :: "i" (SYS_exit));
   printf ("(sc-bad-arg) end\n"); 
   return 0;
 }
diff --git a/grading/userprog/sc-bad-sp.c b/grading/userprog/sc-bad-sp.c
index 1153878..bf92206 100644
--- a/grading/userprog/sc-bad-sp.c
+++ b/grading/userprog/sc-bad-sp.c
@@ -5,7 +5,7 @@ int
 main (void) 
 {
   printf ("(sc-bad-sp) begin\n"); 
-  asm volatile ("mov $0x20101234, %esp; int $0x30");
+  asm volatile ("mov %esp, 0x20101234; int 0x30");
   printf ("(sc-bad-sp) end\n"); 
   return 0;
 }
diff --git a/grading/userprog/sc-boundary.c b/grading/userprog/sc-boundary.c
index 401e437..94c81b9 100644
--- a/grading/userprog/sc-boundary.c
+++ b/grading/userprog/sc-boundary.c
@@ -20,9 +20,7 @@ main (void)
   p--;
   p[0] = SYS_exit;
   p[1] = 42;
-  asm volatile ("mov %0, %%esp; int $0x30"
-                :
-                : "g" (p));
+  asm volatile ("mov %%esp, %0; int 0x30" :: "g" (p));
   printf ("(sc-boundary) failed\n");
   return 1;
 }
diff --git a/solutions/p2.patch b/solutions/p2.patch
index 8f64855..d7b7ca0 100644
--- a/solutions/p2.patch
+++ b/solutions/p2.patch
@@ -640,7 +640,7 @@ diff -u -p -r1.4 syscall.c
 +get_user (uint8_t *dst, const uint8_t *usrc)
 +{
 +  int eax;
-+  asm ("movl $1f, %%eax; movb %2, %%al; movb %%al, %0; 1:"
++  asm ("mov %%eax, offset 1f; mov %%al, %2; mov %0, %%al; 1:"
 +       : "=m" (*dst), "=&a" (eax) : "m" (*usrc));
 +  return eax != 0;
 +}
@@ -652,7 +652,7 @@ diff -u -p -r1.4 syscall.c
 +put_user (uint8_t *udst, uint8_t byte)
 +{
 +  int eax;
-+  asm ("movl $1f, %%eax; movb %b2, %0; 1:"
++  asm ("mov %%eax, offset 1f; mov %0, %b2; 1:"
 +       : "=m" (*udst), "=&a" (eax) : "r" (byte));
 +  return eax != 0;
 +}
diff --git a/src/Make.config b/src/Make.config
index 63d6a22..27f8328 100644
--- a/src/Make.config
+++ b/src/Make.config
@@ -23,7 +23,7 @@ CAT = cat
 
 # Compiler and assembler invocation.
 WARNINGS = -Wall -W -Wstrict-prototypes -Wmissing-prototypes -Wsystem-headers
-CFLAGS = -g -MMD -msoft-float
+CFLAGS = -g -MMD -msoft-float -masm=intel
 ASFLAGS = -Wa,--gstabs -MMD
 
 %.o: %.c
diff --git a/src/lib/kernel/bitmap.c b/src/lib/kernel/bitmap.c
index 9dfded5..abbb85d 100644
--- a/src/lib/kernel/bitmap.c
+++ b/src/lib/kernel/bitmap.c
@@ -156,7 +156,7 @@ bitmap_mark (struct bitmap *b, size_t bit_idx)
   /* This is equivalent to `b->bits[idx] |= mask' except that it
      is guaranteed to be atomic on a uniprocessor machine.  See
      the description of the OR instruction in [IA32-v2b]. */
-  asm ("orl %1, %0" : "=m" (b->bits[idx]) : "r" (mask) : "cc");
+  asm ("or %0, %1" : "=m" (b->bits[idx]) : "r" (mask) : "cc");
 }
 
 /* Atomically sets the bit numbered BIT_IDX in B to false. */
@@ -169,7 +169,7 @@ bitmap_reset (struct bitmap *b, size_t bit_idx)
   /* This is equivalent to `b->bits[idx] &= ~mask' except that it
      is guaranteed to be atomic on a uniprocessor machine.  See
      the description of the AND instruction in [IA32-v2a]. */
-  asm ("andl %1, %0" : "=m" (b->bits[idx]) : "r" (~mask) : "cc");
+  asm ("and %0, %1" : "=m" (b->bits[idx]) : "r" (~mask) : "cc");
 }
 
 /* Atomically toggles the bit numbered IDX in B;
@@ -184,7 +184,7 @@ bitmap_flip (struct bitmap *b, size_t bit_idx)
   /* This is equivalent to `b->bits[idx] ^= mask' except that it
      is guaranteed to be atomic on a uniprocessor machine.  See
      the description of the XOR instruction in [IA32-v2b]. */
-  asm ("xorl %1, %0" : "=m" (b->bits[idx]) : "r" (mask) : "cc");
+  asm ("xor %0, %1" : "=m" (b->bits[idx]) : "r" (mask) : "cc");
 }
 
 /* Returns the value of the bit numbered IDX in B. */
diff --git a/src/lib/user/syscall-stub.S b/src/lib/user/syscall-stub.S
index e71afd5..73afc8d 100644
--- a/src/lib/user/syscall-stub.S
+++ b/src/lib/user/syscall-stub.S
@@ -1,5 +1,6 @@
-.globl syscall
+	.intel_syntax noprefix
+	.globl syscall
 syscall:
-	popl %ecx
-	int $0x30
-	jmpl *%ecx
+	pop ecx
+	int 0x30
+	jmp ecx
diff --git a/src/threads/init.c b/src/threads/init.c
index cf7a896..c17316a 100644
--- a/src/threads/init.c
+++ b/src/threads/init.c
@@ -194,7 +194,7 @@ paging_init (void)
      aka PDBR (page directory base register).  This activates our
      new page tables immediately.  See [IA32-v2a] "MOV--Move
      to/from Control Registers" and [IA32-v3] 3.7.5. */
-  asm volatile ("movl %0,%%cr3" :: "r" (vtop (base_page_dir)));
+  asm volatile ("mov %%cr3, %0" :: "r" (vtop (base_page_dir)));
 }
 
 /* Parses the command line. */
diff --git a/src/threads/interrupt.c b/src/threads/interrupt.c
index c6ca2bd..380544a 100644
--- a/src/threads/interrupt.c
+++ b/src/threads/interrupt.c
@@ -54,7 +54,7 @@ intr_get_level (void)
   /* Push the flags register on the processor stack, then pop the
      value off the stack into `flags'.  See [IA32-v2b] "PUSHF"
      and "POP" and [IA32-v3] 5.8.1. */
-  asm volatile ("pushfl; popl %0" : "=g" (flags));
+  asm volatile ("pushf; pop %0" : "=g" (flags));
 
   return flags & FLAG_IF ? INTR_ON : INTR_OFF;
 }
@@ -368,7 +368,7 @@ intr_dump_frame (const struct intr_frame *f)
      See [IA32-v2a] "MOV--Move to/from Control Registers" and
      [IA32-v3] 5.14 "Interrupt 14--Page Fault Exception
      (#PF)". */
-  asm ("movl %%cr2, %0" : "=r" (cr2));
+  asm ("mov %0, %%cr2" : "=r" (cr2));
 
   printf ("Interrupt %#04x (%s) at eip=%p\n",
           f->vec_no, intr_names[f->vec_no], f->eip);
diff --git a/src/threads/intr-stubs.pl b/src/threads/intr-stubs.pl
index c333260..a5ad9b0 100755
--- a/src/threads/intr-stubs.pl
+++ b/src/threads/intr-stubs.pl
@@ -4,6 +4,7 @@ print <<'EOF';
 #include "threads/loader.h"
 
 	.data
+	.intel_syntax noprefix
 .globl intr_stubs
 intr_stubs:
 EOF
@@ -22,39 +23,39 @@ for $i (0...255) {
     $x = sprintf ("%02x", $i);
     print ".globl intr${x}_stub\n";
     print "intr${x}_stub:\n";
-    print "\tpushl \$0\n"
+    print "\tpush 0\n"
 	if ($i != 8 && $i != 10 && $i != 11
 	    && $i != 13 && $i != 14 && $i != 17);
-    print "\tpushl \$0x$x\n";
+    print "\tpush 0x$x\n";
     print "\tjmp intr_entry\n";
 }
 
 print <<'EOF';
 intr_entry:
 	# Save caller's registers.
-	pushl %ds
-	pushl %es
-	pushal
+	push ds
+	push es
+	pusha
 
 	# Set up kernel environment.
 	cld
-	movl $SEL_KDSEG, %eax
-	movl %eax, %ds
-	movl %eax, %es
+	mov eax, SEL_KDSEG
+	mov ds, eax
+	mov es, eax
 
 	# Call interrupt handler.
-	pushl %esp
+	push esp
 .globl intr_handler
 	call intr_handler
-	addl $4, %esp
+	add esp, 4
 
 .globl intr_exit
 intr_exit:
 	# Restore caller's registers.
-	popal
-	popl %es
-	popl %ds
-	addl $8, %esp
+	popa
+	pop es
+	pop ds
+	add esp, 8
 
         # Return to caller.
 	iret
diff --git a/src/threads/io.h b/src/threads/io.h
index b493299..5395451 100644
--- a/src/threads/io.h
+++ b/src/threads/io.h
@@ -50,7 +50,7 @@ inb (uint16_t port)
 {
   /* See [IA32-v2a] "IN". */
   uint8_t data;
-  asm volatile ("inb %w1,%0" : "=a" (data) : "d" (port));
+  asm volatile ("inb %0, %w1" : "=a" (data) : "d" (port));
   return data;
 }
 
@@ -60,7 +60,7 @@ static inline void
 insb (uint16_t port, void *addr, size_t cnt)
 {
   /* See [IA32-v2a] "INS". */
-  asm volatile ("cld; repne; insb"
+  asm volatile ("cld; repne insb"
                 : "=D" (addr), "=c" (cnt)
                 : "d" (port), "0" (addr), "1" (cnt)
                 : "memory", "cc");
@@ -72,7 +72,7 @@ inw (uint16_t port)
 {
   uint16_t data;
   /* See [IA32-v2a] "IN". */
-  asm volatile ("inw %w1,%0" : "=a" (data) : "d" (port));
+  asm volatile ("inw %0, %w1" : "=a" (data) : "d" (port));
   return data;
 }
 
@@ -82,7 +82,7 @@ static inline void
 insw (uint16_t port, void *addr, size_t cnt)
 {
   /* See [IA32-v2a] "INS". */
-  asm volatile ("cld; repne; insw"
+  asm volatile ("cld; repne insw"
                 : "=D" (addr), "=c" (cnt)
                 : "d" (port), "0" (addr), "1" (cnt)
                 : "memory", "cc");
@@ -94,7 +94,7 @@ inl (uint16_t port)
 {
   /* See [IA32-v2a] "IN". */
   uint32_t data;
-  asm volatile ("inl %w1,%0" : "=a" (data) : "d" (port));
+  asm volatile ("inl %0, %w1" : "=a" (data) : "d" (port));
   return data;
 }
 
@@ -104,7 +104,7 @@ static inline void
 insl (uint16_t port, void *addr, size_t cnt)
 {
   /* See [IA32-v2a] "INS". */
-  asm volatile ("cld; repne; insl"
+  asm volatile ("cld; repne insl"
                 : "=D" (addr), "=c" (cnt)
                 : "d" (port), "0" (addr), "1" (cnt)
                 : "memory", "cc");
@@ -115,7 +115,7 @@ static inline void
 outb (uint16_t port, uint8_t data)
 {
   /* See [IA32-v2b] "OUT". */
-  asm volatile ("outb %0,%w1" : : "a" (data), "d" (port));
+  asm volatile ("outb %w1, %0" : : "a" (data), "d" (port));
 }
 
 /* Writes to PORT each byte of data in the CNT-byte buffer
@@ -124,7 +124,7 @@ static inline void
 outsb (uint16_t port, const void *addr, size_t cnt)
 {
   /* See [IA32-v2b] "OUTS". */
-  asm volatile ("cld; repne; outsb"
+  asm volatile ("cld; repne outsb"
                 : "=S" (addr), "=c" (cnt)
                 : "d" (port), "0" (addr), "1" (cnt)
                 : "cc");
@@ -135,7 +135,7 @@ static inline void
 outw (uint16_t port, uint16_t data)
 {
   /* See [IA32-v2b] "OUT". */
-  asm volatile ("outw %0,%w1" : : "a" (data), "d" (port));
+  asm volatile ("outw %w1, %0" : : "a" (data), "d" (port));
 }
 
 /* Writes to PORT each 16-bit unit (halfword) of data in the
@@ -144,7 +144,7 @@ static inline void
 outsw (uint16_t port, const void *addr, size_t cnt)
 {
   /* See [IA32-v2b] "OUTS". */
-  asm volatile ("cld; repne; outsw"
+  asm volatile ("cld; repne outsw"
                 : "=S" (addr), "=c" (cnt)
                 : "d" (port), "0" (addr), "1" (cnt)
                 : "cc");
@@ -155,7 +155,7 @@ static inline void
 outl (uint16_t port, uint32_t data)
 {
   /* See [IA32-v2b] "OUT". */
-  asm volatile ("outl %0,%w1" : : "a" (data), "d" (port));
+  asm volatile ("outl %w1, %0" : : "a" (data), "d" (port));
 }
 
 /* Writes to PORT each 32-bit unit (word) of data in the CNT-word
@@ -164,7 +164,7 @@ static inline void
 outsl (uint16_t port, const void *addr, size_t cnt)
 {
   /* See [IA32-v2b] "OUTS". */
-  asm volatile ("cld; repne; outsl"
+  asm volatile ("cld; repne outsl"
                 : "=S" (addr), "=c" (cnt)
                 : "d" (port), "0" (addr), "1" (cnt)
                 : "cc");
diff --git a/src/threads/loader.S b/src/threads/loader.S
index d1e8309..811d2b6 100644
--- a/src/threads/loader.S
+++ b/src/threads/loader.S
@@ -40,6 +40,8 @@
 
 #include "threads/loader.h"
 	
+	.intel_syntax noprefix
+	
 #### Kernel loader.
 
 #### This code should be stored in the first sector of the hard disk.
@@ -70,16 +72,16 @@ start:
 
 # Set up data segments and stack.
 
-	subw %ax, %ax
-	movw %ax, %es
-	movw %ax, %ds
+	sub ax, ax
+	mov es, ax
+	mov ds, ax
 
 # Stack grows downward starting from us.
 # We don't ever use the stack so this is strictly speaking
 # unnecessary.
 
-	movw %ax, %ss
-	movw $0x7c00, %sp
+	mov ss, ax
+	mov sp, 0x7c00
 	
 #### Enable A20.  Address line 20 is tied to low when the machine
 #### boots, which prevents addressing memory about 1 MB.  This code
@@ -87,25 +89,25 @@ start:
 	
 # Poll status register while busy.
 
-1:	inb $0x64, %al
-	testb $0x2, %al
+1:	in al, 0x64
+	test al, 0x2
 	jnz 1b
 
 # Send command for writing output port.
 
-	movb $0xd1, %al
-	outb %al, $0x64
+	mov al, 0xd1
+	outb 0x64, al
 
 # Poll status register while busy.
 
-1:	inb $0x64, %al
-	testb $0x2, %al
+1:	in al, 0x64
+	test al, 0x2
 	jnz 1b
 
 # Enable A20 line.
 
-	movb $0xdf, %al
-	outb %al, $0x60
+	mov al, 0xdf
+	out 0x60, al
 
 #### Get memory size, via interrupt 15h function 88h.  Returns CF
 #### clear if successful, with AX = (kB of physical memory) - 1024.
@@ -113,57 +115,57 @@ start:
 #### for our purposes.  We cap memory at 64 MB because that's all we
 #### prepare page tables for, below.
 	
-	movb $0x88, %ah
-	int $0x15
+	mov ah, 0x88
+	int 0x15
 	jc panic
-	addl $1024, %eax	# Total kB memory
-	cmp $0x10000, %eax	# Cap at 64 MB
+	add eax, 1024		# Total kB memory
+	cmp eax, 0x10000	# Cap at 64 MB
 	jbe 1f
-	mov $0x10000, %eax
-1:	shrl $2, %eax		# Total 4 kB pages
-	movl %eax, ram_pages
+	mov eax, 0x10000
+1:	shr eax, 2		# Total 4 kB pages
+	mov ram_pages, eax 
 	
 #### Create temporary page directory and page table and set page
 #### directory base register.
 
 # Create page directory at 64 kB and fill with zeroes.
-	mov $0x1000, %ax
-	mov %ax, %es
-	subl %eax, %eax
-	subl %edi, %edi
-	movl $0x400, %ecx
-	rep stosl
+	mov ax, 0x1000
+	mov es, ax
+	sub eax, eax
+	sub edi, edi
+	mov ecx, 0x400
+	rep stosd
 
 # Add PDEs to point to PTEs for the first 64 MB of RAM.
 # Also add identical PDEs starting at LOADER_PHYS_BASE.
-# See [IA32-v3] section 3.7.6 for a description of the bits in %eax.
-
-	movl $0x11007, %eax
-	movl $0x11, %ecx
-	subl %edi, %edi
-1:	movl %eax, %es:(%di)
-	movl %eax, %es:LOADER_PHYS_BASE >> 20(%di)
-	addw $4, %di
-	addl $0x1000, %eax
+# See [IA32-v3] section 3.7.6 for a description of the bits in eax.
+
+	mov eax, 0x11007
+	mov ecx, 0x11
+	sub edi, edi
+1:	mov es:[di], eax
+	mov es:LOADER_PHYS_BASE / 1024 / 1024[di], eax 
+	add di, 4
+	add eax, 0x1000
 	loop 1b
 
 # Set up one-to-map linear to physical map for the first 64 MB of RAM.
-# See [IA32-v3] section 3.7.6 for a description of the bits in %eax.
-
-	movw $0x1100, %ax
-	movw %ax, %es
-	movl $0x7, %eax
-	movl $0x4000, %ecx
-	subl %edi, %edi
-1:	movl %eax, %es:(%di)
-	addw $4, %di
-	addl $0x1000, %eax
+# See [IA32-v3] section 3.7.6 for a description of the bits in eax.
+
+	mov ax, 0x1100
+	mov es, ax
+	mov eax, 0x7
+	mov ecx, 0x4000
+	sub edi, edi
+1:	mov es:[di], eax 
+	add di, 4 
+	add eax, 0x1000
 	loop 1b
 
 # Set page directory base register.
 
-	movl $0x10000, %eax
-	movl %eax, %cr3
+	mov eax, 0x10000
+	mov cr3, eax
 	
 #### Switch to protected mode.
 
@@ -185,18 +187,18 @@ start:
 #    EM (Emulation): forces floating-point instructions to trap.
 #       We don't support floating point. 
 	
-	movl %cr0, %eax
-	orl $CR0_PE | CR0_PG | CR0_WP | CR0_EM, %eax
-	movl %eax, %cr0
+	mov eax, cr0
+	or eax, CR0_PE + CR0_PG + CR0_WP + CR0_EM
+	mov cr0, eax
 	
 # We're now in protected mode in a 16-bit segment.  The CPU still has
-# the real-mode code segment cached in %cs's segment descriptor.  We
-# need to reload %cs, and the easiest way is to use a far jump.
+# the real-mode code segment cached in cs's segment descriptor.  We
+# need to reload cs, and the easiest way is to use a far jump.
 # Because we're not in a 32-bit segment the data32 prefix is needed to
 # jump to a 32-bit offset.
 
-	data32 ljmp $SEL_KCSEG, $1f + LOADER_PHYS_BASE
-	
+	data32 ljmp SEL_KCSEG, 1f + LOADER_PHYS_BASE
+
 # We're now in protected mode in a 32-bit segment.
 
 	.code32
@@ -204,83 +206,83 @@ start:
 # Reload all the other segment registers and the stack pointer to
 # point into our new GDT.
 
-1:	movw $SEL_KDSEG, %ax
-	movw %ax, %ds		
-	movw %ax, %es		
-	movw %ax, %fs		
-	movw %ax, %gs		
-	movw %ax, %ss
-	movl $LOADER_PHYS_BASE + 0x30000, %esp
+1:	mov ax, SEL_KDSEG
+	mov ds, ax		
+	mov es, ax		
+	mov fs, ax		
+	mov gs, ax		
+	mov ss, ax
+	mov esp, LOADER_PHYS_BASE + 0x30000
 
 #### Load kernel starting at physical address LOADER_KERN_BASE by
 #### frobbing the IDE controller directly.
 
-	movl $1, %ebx
-	movl $LOADER_KERN_BASE + LOADER_PHYS_BASE, %edi
+	mov ebx, 1
+	mov edi, LOADER_KERN_BASE + LOADER_PHYS_BASE
 read_sector:
 
 # Poll status register while controller busy.
 
-	movl $0x1f7, %edx
-1:	inb %dx, %al
-	testb $0x80, %al
+	mov edx, 0x1f7
+1:	in al, dx
+	test al, 0x80
 	jnz 1b
 
 # Read a single sector.
 
-	movl $0x1f2, %edx
-	movb $1, %al
-	outb %al, %dx
+	mov edx, 0x1f2
+	mov al, 1 
+	out dx, al
 
 # Sector number to write in low 28 bits.
 # LBA mode, device 0 in top 4 bits.
 
-	movl %ebx, %eax
-	andl $0x0fffffff, %eax
-	orl $0xe0000000, %eax
+	mov eax, ebx
+	and eax, 0x0fffffff
+	or eax, 0xe0000000
 
-# Dump %eax to ports 0x1f3...0x1f6.
+# Dump eax to ports 0x1f3...0x1f6.
 
-	movl $4, %ecx
-1:	incw %dx
-	outb %al, %dx
-	shrl $8, %eax
+	mov ecx, 4
+1:	inc dx
+	out dx, al
+	shr eax, 8
 	loop 1b
 
 # READ command to command register.
 
-	incw %dx
-	movb $0x20, %al
-	outb %al, %dx
+	inc dx
+	mov al, 0x20
+	out dx, al
 
 # Poll status register while controller busy.
 
-1:	inb %dx, %al
-	testb $0x80, %al
+1:	in al, dx
+	test al, 0x80
 	jnz 1b
 
 # Poll status register until data ready.
 
-1:	inb %dx, %al
-	testb $0x08, %al
+1:	in al, dx
+	test al, 0x08
 	jz 1b
 
 # Transfer sector.
 
-	movl $256, %ecx
-	movl $0x1f0, %edx
+	mov ecx, 256
+	mov edx, 0x1f0
 	rep insw
 
 # Next sector.
 
-	incl %ebx
-	cmpl $KERNEL_LOAD_PAGES*8 + 1, %ebx
+	inc ebx
+	cmp ebx, KERNEL_LOAD_PAGES*8 + 1
 	jnz read_sector
 
 #### Jump to kernel entry point.
 
-	movl $LOADER_PHYS_BASE + LOADER_KERN_BASE, %eax
-	call *%eax
+	mov eax, LOADER_PHYS_BASE + LOADER_KERN_BASE
+	call eax
 	jmp panic
 
 #### GDT
@@ -298,13 +300,13 @@ gdtdesc:
 #### Print panicmsg (with help from the BIOS) and spin.
 
 panic:  .code16			# We only panic in real mode.
-	movw $panicmsg, %si
-	movb $0xe, %ah
-	subb %bh, %bh
+	mov si, offset panicmsg
+	mov ah, 0xe
+	sub bh, bh
 1:	lodsb
-	test %al, %al
+	test al, al
 2:	jz 2b			# Spin.
-	int $0x10
+	int 0x10
 	jmp 1b
 
 panicmsg:
diff --git a/src/threads/switch.S b/src/threads/switch.S
index 374da9e..4f0d412 100644
--- a/src/threads/switch.S
+++ b/src/threads/switch.S
@@ -12,52 +12,54 @@
 #### restore the registers.  As part of switching stacks we record the
 #### current stack pointer in CUR's thread structure.
 
+	.intel_syntax noprefix
+
 .globl switch_threads 
 switch_threads:
 	# Save caller's register state.
 	#
-	# Note that the SVR4 ABI allows us to destroy %eax, %ecx, %edx,
-	# but requires us to preserve %ebx, %ebp, %esi, %edi.  See
+	# Note that the SVR4 ABI allows us to destroy eax, ecx, edx,
+	# but requires us to preserve ebx, ebp, esi, edi.  See
 	# [SysV-ABI-386] pages 3-11 and 3-12 for details.
 	#
 	# This stack frame must match the one set up by thread_create().
-	pushl %ebx
-	pushl %ebp
-	pushl %esi
-	pushl %edi
+	push ebx
+	push ebp
+	push esi
+	push edi
 
 	# Get offsetof (struct thread, stack).
 .globl thread_stack_ofs
-	mov thread_stack_ofs, %edx
+	mov edx, thread_stack_ofs
 
 	# Save current stack pointer to old thread's stack, if any.
-	movl SWITCH_CUR(%esp), %eax
-	test %eax, %eax
+	mov eax, SWITCH_CUR[esp]
+	test eax, eax
 	jz 1f
-	movl %esp, (%eax,%edx,1)
+	mov [eax + edx], esp
 1:
 
 	# Restore stack pointer from new thread's stack.
-	movl SWITCH_NEXT(%esp), %ecx
-	movl (%ecx,%edx,1), %esp
+	mov ecx, SWITCH_NEXT[esp]
+	mov esp, [ecx + edx]
 
 	# Restore caller's register state.
-	popl %edi
-	popl %esi
-	popl %ebp
-	popl %ebx
+	pop edi
+	pop esi
+	pop ebp
+	pop ebx
         ret
 
 .globl switch_entry
 switch_entry:
 	# Discard switch_threads() arguments.
-	addl $8, %esp
+	add esp, 8
 
 	# Call schedule_tail(prev).
-	pushl %eax
+	push eax
 .globl schedule_tail
 	call schedule_tail
-	addl $4, %esp
+	add esp, 4
 
 	# Start thread proper.
 	ret
diff --git a/src/threads/thread.c b/src/threads/thread.c
index 0a606b7..01ce7d3 100644
--- a/src/threads/thread.c
+++ b/src/threads/thread.c
@@ -312,7 +312,7 @@ running_thread (void)
      down to the start of a page.  Because `struct thread' is
      always at the beginning of a page and the stack pointer is
      somewhere in the middle, this locates the curent thread. */
-  asm ("movl %%esp, %0\n" : "=g" (esp));
+  asm ("mov %0, %%esp" : "=g" (esp));
   return pg_round_down (esp);
 }
 
diff --git a/src/userprog/exception.c b/src/userprog/exception.c
index 745adaa..dcfccb8 100644
--- a/src/userprog/exception.c
+++ b/src/userprog/exception.c
@@ -136,7 +136,7 @@ page_fault (struct intr_frame *f)
      See [IA32-v2a] "MOV--Move to/from Control Registers" and
      [IA32-v3] 5.14 "Interrupt 14--Page Fault Exception
      (#PF)". */
-  asm ("movl %%cr2, %0" : "=r" (fault_addr));
+  asm ("mov %0, %%cr2" : "=r" (fault_addr));
 
   /* Turn interrupts back on (they were only off so that we could
      be assured of reading CR2 before it changed). */
diff --git a/src/userprog/pagedir.c b/src/userprog/pagedir.c
index c0a015a..3ad8123 100644
--- a/src/userprog/pagedir.c
+++ b/src/userprog/pagedir.c
@@ -192,7 +192,7 @@ pagedir_activate (uint32_t *pd)
      aka PDBR (page directory base register).  This activates our
      new page tables immediately.  See [IA32-v2a] "MOV--Move
      to/from Control Registers" and [IA32-v3] 3.7.5. */
-  asm volatile ("movl %0,%%cr3" :: "r" (vtop (pd)));
+  asm volatile ("mov %%cr3, %0" :: "r" (vtop (pd)));
 }
 
 /* Returns the currently active page directory. */
@@ -204,6 +204,6 @@ active_pd (void)
      See [IA32-v2a] "MOV--Move to/from Control Registers" and
      [IA32-v3] 3.7.5. */
   uint32_t *pd;
-  asm ("movl %%cr3,%0" : "=r" (pd));
+  asm ("mov %0, %%cr3" : "=r" (pd));
   return pd;
 }
diff --git a/src/userprog/process.c b/src/userprog/process.c
index 90ff18b..b9a199e 100644
--- a/src/userprog/process.c
+++ b/src/userprog/process.c
@@ -75,10 +75,7 @@ execute_thread (void *filename_)
      arguments on the stack in the form of a `struct intr_frame',
      we just point the stack pointer (%esp) to our stack frame
      and jump to it. */
-  asm ("mov %0, %%esp\n"
-       "jmp intr_exit\n"
-       : /* no outputs */
-       : "g" (&if_));
+  asm ("mov %%esp, %0; jmp intr_exit" :: "g" (&if_));
   NOT_REACHED ();
 }