X-Git-Url: https://pintos-os.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fuserprog%2Fpagedir.c;h=3f0e9fb47c1217c8bbe0266f8a5b6b7a9e130e0e;hb=47fcd26fa98f931f15e5961998b2437e2789f8b3;hp=f26496d79467aa316e5b0f13953c2c07eb6d4fa4;hpb=8382bdd7884a6d38f7529e0517dd9a7083f4ce73;p=pintos-anon

diff --git a/src/userprog/pagedir.c b/src/userprog/pagedir.c
index f26496d..3f0e9fb 100644
--- a/src/userprog/pagedir.c
+++ b/src/userprog/pagedir.c
@@ -6,6 +6,8 @@
 #include "threads/mmu.h"
 #include "threads/palloc.h"
 
+static uint32_t *active_pd (void);
+
 /* Creates a new page directory that has mappings for kernel
    virtual addresses, but none for user virtual addresses.
    Returns the new page directory, or a null pointer if memory
@@ -43,10 +45,11 @@ pagedir_destroy (uint32_t *pd)
   palloc_free_page (pd);
 }
 
-/* Returns the mapping of user virtual address UADDR in page
-   directory PD into a kernel virtual address.
-   If UADDR is unmapped, behavior varies based on CREATE:
-   if CREATE is true, then a new, zeroed page is created and a
+/* Returns the address of the page table entry for user virtual
+   address UADDR in page directory PD.
+   If PD does not have a page table for UADDR, behavior varies
+   based on CREATE:
+   if CREATE is true, then a new page table is created and a
    pointer into it is returned,
    otherwise a null pointer is returned.
    Also returns a null pointer if UADDR is a kernel address. */
@@ -118,7 +121,63 @@ void *
 pagedir_get_page (uint32_t *pd, const void *uaddr) 
 {
   uint32_t *pte = lookup_page (pd, (void *) uaddr, false);
-  return pte != NULL && *pte != 0 ? pte_get_page (*pte) : NULL;
+  return (pte != NULL && *pte != 0
+          ? (uint8_t *) pte_get_page (*pte) + pg_ofs (uaddr)
+          : NULL);
+}
+
+/* Clears any mapping for user virtual address UPAGE in page
+   directory PD.
+   UPAGE need not already be mapped. */
+void
+pagedir_clear_page (uint32_t *pd, void *upage) 
+{
+  uint32_t *pte = lookup_page (pd, upage, false);
+  if (pte != NULL && *pte != 0)
+    {
+      *pte = 0;
+
+      if (active_pd () == pd) 
+        {
+          /* We cleared a page-table entry in the active page
+             table, so we have to invalidate the TLB.  See
+             [IA32-v3], section 3.11. */
+          pagedir_activate (pd);
+        }
+    }
+
+}
+
+/* Returns true if the PTE for user virtual page UPAGE in PD is
+   dirty, that is, if the page has been modified since the PTE
+   was installed.
+   Returns false if PD contains no PDE for UPAGE. */
+bool
+pagedir_test_dirty (uint32_t *pd, const void *upage) 
+{
+  uint32_t *pte = lookup_page (pd, (void *) upage, false);
+  return pte != NULL && (*pte & PG_D) != 0;
+}
+
+/* Returns true if the PTE for user virtual page UPAGE in PD has
+   been accessed recently, that is, between the time the PTE was
+   installed and the last time it was cleared.
+   Returns false if PD contains no PDE for UPAGE. */
+bool
+pagedir_test_accessed (uint32_t *pd, const void *upage) 
+{
+  uint32_t *pte = lookup_page (pd, (void *) upage, false);
+  return pte != NULL && (*pte & PG_A) != 0;
+}
+
+/* Resets the accessed bit in the PTE for user virtual page UPAGE
+   in PD. */
+void
+pagedir_clear_accessed (uint32_t *pd, const void *upage) 
+{
+  uint32_t *pte = lookup_page (pd, (void *) upage, false);
+  if (pte != NULL) 
+    *pte &= ~(uint32_t) PG_A;
 }
 
 /* Loads page directory PD into the CPU's page directory base
@@ -128,5 +187,23 @@ pagedir_activate (uint32_t *pd)
 {
   if (pd == NULL)
     pd = base_page_dir;
+
+  /* Store the physical address of the page directory into CR3
+     aka PDBR (page directory base register).  This activates our
+     new page tables immediately.  See [IA32-v2a] "MOV--Move
+     to/from Control Registers" and [IA32-v3] 3.7.5. */
   asm volatile ("movl %0,%%cr3" :: "r" (vtop (pd)));
 }
+
+/* Returns the currently active page directory. */
+static uint32_t *
+active_pd (void) 
+{
+  uint32_t *pd;
+
+  /* Copy CR3, the page directory base register (PDBR), into `pd'
+     for us to examine.  See [IA32-v2a] "MOV--Move to/from
+     Control Registers" and [IA32-v3] 3.7.5. */
+  asm ("movl %%cr3,%0" : "=r" (pd));
+  return pd;
+}