X-Git-Url: https://pintos-os.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fthreads%2Finterrupt.c;h=24539e6ccc11a2839abd88319deee2208c015049;hb=8fff557107b6a3efec0000ce98904450c1de3648;hp=27f470861a22de11b725475b731d2a11afdfafcc;hpb=e81af6fff9570e6f3f2b13bb9ad54cc17f25aa50;p=pintos-anon

diff --git a/src/threads/interrupt.c b/src/threads/interrupt.c
index 27f4708..24539e6 100644
--- a/src/threads/interrupt.c
+++ b/src/threads/interrupt.c
@@ -20,6 +20,14 @@
 #define IRQ_CASCADE0   2
 #define IRQ_CASCADE1   9
 
+/* Programmable Interrupt Controller (PIC) registers.
+   A PC has two PICs, called the master and slave PICs, with the
+   slave attached ("cascaded") to the master IRQ line 2. */
+#define PIC0_CTRL	0x20    /* Master PIC control register address. */
+#define PIC0_DATA	0x21    /* Master PIC data register address. */
+#define PIC1_CTRL	0xa0    /* Slave PIC control register address. */
+#define PIC1_DATA	0xa1    /* Slave PIC data register address. */
+
 /* Number of x86 interrupts. */
 #define INTR_CNT 256