#include <stddef.h>
#include <string.h>
#include "threads/init.h"
-#include "threads/mmu.h"
+#include "threads/pte.h"
#include "threads/palloc.h"
static uint32_t *active_pd (void);
ASSERT (pd != base_page_dir);
for (pde = pd; pde < pd + pd_no (PHYS_BASE); pde++)
- if (*pde & PG_P)
+ if (*pde & PTE_P)
{
uint32_t *pt = pde_get_pt (*pde);
uint32_t *pte;
for (pte = pt; pte < pt + PGSIZE / sizeof *pte; pte++)
- if (*pte & PG_P)
+ if (*pte & PTE_P)
palloc_free_page (pte_get_page (*pte));
palloc_free_page (pt);
}
return &pt[pt_no (vaddr)];
}
-/* Adds a mapping from user virtual page UPAGE to kernel virtual
- address KPAGE in page directory PD.
+/* Adds a mapping in page directory PD from user virtual page
+ UPAGE to the physical frame identified by kernel virtual
+ address KPAGE.
UPAGE must not already be mapped.
+ KPAGE should probably be a page obtained from the user pool
+ with palloc_get_page().
If WRITABLE is true, the new page is read/write;
otherwise it is read-only.
Returns true if successful, false if memory allocation
failed. */
bool
-pagedir_set_page (uint32_t *pd, void *upage, void *kpage,
- bool writable)
+pagedir_set_page (uint32_t *pd, void *upage, void *kpage, bool writable)
{
uint32_t *pte;
if (pte != NULL)
{
- ASSERT ((*pte & PG_P) == 0);
+ ASSERT ((*pte & PTE_P) == 0);
*pte = pte_create_user (kpage, writable);
return true;
}
return false;
}
-/* Returns the kernel virtual address that user virtual address
- UADDR is mapped to in PD, or a null pointer if UADDR is not
- present. */
+/* Looks up the physical address that corresponds to user virtual
+ address UADDR in PD. Returns the kernel virtual address
+ corresponding to that physical address, or a null pointer if
+ UADDR is unmapped. */
void *
pagedir_get_page (uint32_t *pd, const void *uaddr)
{
ASSERT (is_user_vaddr (uaddr));
pte = lookup_page (pd, uaddr, false);
- if (pte != NULL && (*pte & PG_P) != 0)
+ if (pte != NULL && (*pte & PTE_P) != 0)
return pte_get_page (*pte) + pg_ofs (uaddr);
else
return NULL;
ASSERT (is_user_vaddr (upage));
pte = lookup_page (pd, upage, false);
- if (pte != NULL && (*pte & PG_P) != 0)
+ if (pte != NULL && (*pte & PTE_P) != 0)
{
- *pte &= ~PG_P;
+ *pte &= ~PTE_P;
invalidate_pagedir (pd);
}
}
pagedir_is_dirty (uint32_t *pd, const void *vpage)
{
uint32_t *pte = lookup_page (pd, vpage, false);
- return pte != NULL && (*pte & PG_D) != 0;
+ return pte != NULL && (*pte & PTE_D) != 0;
}
/* Set the dirty bit to DIRTY in the PTE for virtual page VPAGE
if (pte != NULL)
{
if (dirty)
- *pte |= PG_D;
+ *pte |= PTE_D;
else
{
- *pte &= ~(uint32_t) PG_D;
+ *pte &= ~(uint32_t) PTE_D;
invalidate_pagedir (pd);
}
}
pagedir_is_accessed (uint32_t *pd, const void *vpage)
{
uint32_t *pte = lookup_page (pd, vpage, false);
- return pte != NULL && (*pte & PG_A) != 0;
+ return pte != NULL && (*pte & PTE_A) != 0;
}
/* Sets the accessed bit to ACCESSED in the PTE for virtual page
if (pte != NULL)
{
if (accessed)
- *pte |= PG_A;
+ *pte |= PTE_A;
else
{
- *pte &= ~(uint32_t) PG_A;
+ *pte &= ~(uint32_t) PTE_A;
invalidate_pagedir (pd);
}
}
/* Store the physical address of the page directory into CR3
aka PDBR (page directory base register). This activates our
new page tables immediately. See [IA32-v2a] "MOV--Move
- to/from Control Registers" and [IA32-v3] 3.7.5. */
- asm volatile ("mov %%cr3, %0" :: "r" (vtop (pd)));
+ to/from Control Registers" and [IA32-v3a] 3.7.5 "Base
+ Address of the Page Directory". */
+ asm volatile ("movl %0, %%cr3" : : "r" (vtop (pd)) : "memory");
}
/* Returns the currently active page directory. */
/* Copy CR3, the page directory base register (PDBR), into
`pd'.
See [IA32-v2a] "MOV--Move to/from Control Registers" and
- [IA32-v3] 3.7.5. */
+ [IA32-v3a] 3.7.5 "Base Address of the Page Directory". */
uintptr_t pd;
- asm volatile ("mov %0, %%cr3" : "=r" (pd));
+ asm volatile ("movl %%cr3, %0" : "=r" (pd));
return ptov (pd);
}
{
if (active_pd () == pd)
{
- /* We cleared a page-table entry in the active page
- table, so we have to invalidate the TLB. See
- [IA32-v3], section 3.11. */
+ /* Re-activating PD clears the TLB. See [IA32-v3a] 3.12
+ "Translation Lookaside Buffers (TLBs)". */
pagedir_activate (pd);
}
}