#define CR0_PG 0x80000000 /* Paging. */
#define CR0_WP 0x00010000 /* Write-Protect enable in kernel mode. */
-# Code runs in real mode, which is a 16-bit segment.
.globl start
start:
+
+# Code runs in real mode, which is a 16-bit segment.
.code16
-# Disable interrupts.
-# String instructions go upward.
+# Disable interrupts, because we will not be prepared to handle them
+# in protected mode until much later.
+# String instructions go upward (e.g. for "rep stosl" below).
cli
cld
# Add PDEs to point to PTEs for the first 64 MB of RAM.
# Also add identical PDEs starting at LOADER_PHYS_BASE.
-# See [IA32-v3] section 3.7.6 for a description of the bits in %eax.
+# See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries"
+# for a description of the bits in %eax.
+
movl $0x11007, %eax
movl $0x11, %ecx
loop 1b
# Set up one-to-map linear to physical map for the first 64 MB of RAM.
-# See [IA32-v3] section 3.7.6 for a description of the bits in %eax.
+# See [IA32-v3a] section 3.7.6 "Page-Directory and Page-Table Entries"
+# for a description of the bits in %eax.
movw $0x1100, %ax
movw %ax, %es
movl $1, %ebx
movl $LOADER_KERN_BASE + LOADER_PHYS_BASE, %edi
+
+# Disable interrupt delivery by IDE controller, because we will be
+# polling for data.
+# (If we don't do this, Bochs 2.2.6 will never deliver any IDE
+# interrupt to us later after we reset the interrupt controller during
+# boot, even if we also reset the IDE controller.)
+
+ movw $0x3f6, %dx
+ movb $0x02, %al
+ outb %al, %dx
+
read_sector:
# Poll status register while controller busy.