#include "threads/interrupt.h"
#include "threads/synch.h"
+/* The code in this file is an interface to an ATA (IDE)
+ controller. It attempts to comply to [ATA-3]. */
+
/* ATA command block port addresses. */
#define reg_data(CHANNEL) ((CHANNEL)->reg_base + 0) /* Data. */
#define reg_error(CHANNEL) ((CHANNEL)->reg_base + 1) /* Error. */
int dev_no;
/* Initialize channel. */
- snprintf (c->name, sizeof c->name, "hd%zd", chan_no);
+ snprintf (c->name, sizeof c->name, "hd%zu", chan_no);
switch (chan_no)
{
case 0:
/* Issue soft reset sequence, which selects device 0 as a side effect.
Also enable interrupts. */
outb (reg_ctl (c), 0);
- timer_sleep (timer_us2ticks (10));
+ timer_usleep (10);
outb (reg_ctl (c), CTL_SRST);
- timer_sleep (timer_us2ticks (10));
+ timer_usleep (10);
outb (reg_ctl (c), 0);
- timer_sleep (timer_ms2ticks (150));
+ timer_msleep (150);
/* Wait for device 0 to clear BSY. */
if (present[0])
{
if (inb (reg_nsect (c)) == 1 && inb (reg_lbal (c)) == 1)
break;
- timer_sleep (timer_ms2ticks (10));
+ timer_msleep (10);
}
wait_while_busy (&c->devices[1]);
}
{
if ((inb (reg_status (d->channel)) & (STA_BSY | STA_DRQ)) == 0)
return;
- timer_sleep (timer_us2ticks (10));
+ timer_usleep (10);
}
printf ("%s: idle timeout\n", d->name);
printf ("ok\n");
return (inb (reg_alt_status (c)) & STA_DRQ) != 0;
}
- timer_sleep (timer_ms2ticks (10));
+ timer_msleep (10);
}
printf ("failed\n");
dev |= DEV_DEV;
outb (reg_device (c), dev);
inb (reg_alt_status (c));
- timer_sleep (timer_ns2ticks (400));
+ timer_nsleep (400);
}
/* Select disk D in its channel, as select_device(), but wait for