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Hardware Level VGA and SVGA Video Programming Information
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External Regsters
The External Registers (sometimes
called the General Registers) each have their own unique I/O location in
the VGA, although sometimes the Read Port differs from the Write port,
and some are Read-only.. See the Accessing the VGA
Registers section for more detals.
-
Port 3CCh/3C2h -- Miscellaneous Output Register
-
Port 3CAh/3xAh -- Feature Control Register
-
Port 3C2h -- Input Status #0 Register
-
Port 3xAh -- Input Status #1 Register
Miscellaneous Output Register
(Read at 3CCh, Write at 3C2h)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| VSYNCP |
HSYNCP |
O/E Page |
|
Clock Select |
RAM En. |
I/OAS |
VSYNCP -- Vertical Sync Polarity
"Determines the polarity of the vertical sync pulse and can be used
(with HSP) to control the vertical size of the display by utilizing the
autosynchronization feature of VGA displays.
= 0 selects a positive vertical retrace sync pulse."
HSYNCP -- Horizontal Sync Polarity
"Determines the polarity of the horizontal sync pulse.
= 0 selects a positive horizontal retrace sync pulse."
O/E Page -- Odd/Even Page Select
"Selects the upper/lower 64K page of memory when the system is in
an eve/odd mode (modes 0,1,2,3,7).
= 0 selects the low page
= 1 selects the high page"
-
Clock Select
This field controls the selection of the dot clocks used in driving
the display timing. The standard hardware has 2 clocks available
to it, nominally 25 Mhz and 28 Mhz. It is possible that there may
be other "external" clocks that can be selected by programming this register
with the undefined values. The possible valuse of this register are:
-
00 -- select 25 Mhz clock (used for 320/640 pixel wide modes)
-
01 -- select 28 Mhz clock (used for 360/720 pixel wide modes)
-
10 -- undefined (possible external clock)
-
11 -- undefined (possible external clock)
RAM En. -- RAM Enable
"Controls system access to the display buffer.
= 0 disables address decode for the display buffer from the
system
= 1 enables address decode for the display buffer from the
system"
I/OAS -- Input/Output Address Select
"This bit selects the CRT controller addresses. When set to 0, this
bit sets the CRT controller addresses to 0x03Bx and the address for the
Input Status Register 1 to 0x03BA for compatibility withthe monochrome
adapter. When set to 1, this bit sets CRT controller addresses to
0x03Dx and the Input Status Register 1 address to 0x03DA for compatibility
with the color/graphics adapter. The Write addresses to the Feature Control
register are affected in the same manner."
Feature Control Register (Read
at 3CAh, Write at 3BAh (mono) or 3DAh (color))
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
FC1 |
FC0 |
-
FC1 -- Feature Control bit 1
"All bits are reserved."
-
FC2 -- Feature Control bit 0
"All bits are reserved."
Input Status #0 Register (Read-only
at 3C2h)
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
SS |
|
|
|
|
SS - Switch Sense
"Returns the status of the four sense switches as selected by the
CS field of the Miscellaneous Output Register."
Input Status #1 Register (Read
at 3BAh (mono) or 3DAh (color))
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
VRetrace |
|
|
DD |
VRetrace -- Vertical Retrace
"When set to 1, this bit indicates that the display is in a vertical
retrace interval.This bit can be programmed, through the Vertical Retrace
End register, to generate an interrupt at the start of the vertical retrace."
DD -- Display Disabled
"When set to 1, this bit indicates a horizontal or vertical retrace
interval. This bit is the real-time status of the inverted 'display enable'
signal. Programs have used this status bit to restrict screen updates to
the inactive display intervals in order to reduce screen flicker. The video
subsystem is designed to eliminate this software requirement; screen updates
may be made at any time without screen degradation."
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All pages are Copyright © 1997, 1998, J. D. Neal, except where
noted. Permission for utilization and distribution is subject to the terms
of the FreeVGA Project Copyright License.